Linear Transconductance Research Articles

QFGMOS and FGMOS based low-voltage high performance MI-OTA

In this paper, two multiple-input operational transconductance amplifiers (MI-OTA) have been proposed. The proposed-I MI-OTA utilizes FGMOS technology to operate at low supply voltage. This proposed MI-OTA provides the flexibility of varying the transconductance of the device by changing the biasing voltage while closely maintaining the linear input voltage range of conventional MI-OTA. However, it operates at lower bandwidth, input resistance and output resistance. To overcome the drawbacks of proposed-I MI-OTA, QFGMOS based MI-OTA has been proposed. This proposed-II MI-OTA operates at low supply voltage while maintaining the high performance behavior of conventional MI-OTA. The proposed circuits have been simulated with the help of TSMC based 0.18 µm CMOS technology using Mentor Graphics Eldospice. Supply voltage of ± 1 V has been used to simulate the proposed circuits and validate their performance characteristics. For input voltage variation of − 0.6 and 0.6 V, approximately linear transconductance in the range of 195.8527 to 187.9106 and 401.419 to 201.6030 µA/V was observed in proposed-I and proposed-II MI-OTAs respectively. Simulated values for bandwidth, input resistance, output resistance and power consumed have been observed to be 110.07 MHz, 4.989 GΩ, 0.8791 MΩ and 1.8154 mW for proposed-I MI-OTA and 127.56 MHz, 209.872 GΩ, 2.6218 MΩ and 1.466 mW for proposed-II MI-OTA respectively.

A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

Simplified treatment of the transconductance linearization problem employing any number of coupled differential pairs

SummaryThis paper is a step toward a rigorous mathematical analysis of the transconductance linearization problem. Using the apparatus of approximation theory, we show that the transconductance linearization problem is a function approximation problem. We elaborate two separate methods for solving this problem: (i) Padé and (ii) Padé‐type methods. Both methods are of the maximum flatness type because they are particular cases of the generalized Taylor series method. As a by‐product of our mathematical analysis, we develop new linearization techniques. In particular, we show that maximum flatness can be derived by the Padé‐type method by simply choosing distinct gate voltages. This characterizes new extensions of known design guidelines.

A wide linear range CMOS OTA and its application in continuous-time filters

In this paper, we have proposed a highly linear Operational Transconductance Amplifier (OTA) with wide linear input range. The proposed OTA utilizes conventional source degeneration with an auxiliary differential pair which increases the linear range significantly by reducing the distortion components. The proposed OTA is targeted for current mode circuit applications including low-frequency continuous time filters. A second-order fully differential filter architecture is also implemented by using this proposed OTA. The linear OTA and the filter are implemented in SCL 180 nm CMOS process technology with 1.8 V supply voltage. The proposed OTA achieves third order harmonic distortion ($${\textit{HD}}_3$$) of $$-\,74.3$$ dB, inter modulation distortion ($${\textit{IM}}_3$$) of $$-\,75.5$$ dB for $$600\,\hbox{mV}_{p-p}$$ differential input with 1 MHz signal frequency and a linear range of 0.9 V for 1% transconductance variation. The filter is designed for 100 kHz cutoff frequency and achieves $${\textit{HD}}_3$$ of $$-\,68.75$$ dB and $${\textit{IM}}_3$$ of $$-\,64.3$$ dB for $$300\,\hbox{mV}_{p-p}$$, 10 kHz input signal.

Design of low power fault tolerant flash ADC for instrumentation applications

Technological growth has remarkably put their efforts in making the electronic world a powerful one. Analog to digital converter (ADC) is said to be ancestor in the field of transforming analog information into digital form. It is a necessary component in RF and Mixed signal designs. This paper suggests both neither compact NOR based CMOS Linear Tuneable Transconductance Element (NOR-LTE) Comparator and Dynamic Priority Encoder (DPE). The NOR-LTE comparator reduces the power utilization and offset error, which improves the Power Supply Rejection Ratio (PSRR) of an overall circuit design. Dynamic Priority Encoder curtails the transistor count prescribed for Flash ADC. The proposed Fault Tolerant Flash ADC (FT-FADC) framework is implemented using Tanner EDA with 0.25 ​ ​μm CMOS technology. The above suggested FT- FADC achieves 3.44-bit ENOB at 1.5 ​V supply for 500 ​MHz Resolution Bandwidth (RSB). Due to high sampling rate 1.3 ​GS/s it upgrades the throughput rate by 60% and reduces the utilization of power by 47%.

Interface charge engineering in AlTiO/AlGaN/GaN metal–insulator–semiconductor devices

Toward interface charge engineering in AlTiO/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, we systematically investigated insulator-semiconductor interface fixed charges depending on the composition of the AlTiO gate insulator obtained by atomic layer deposition. By evaluating the positive interface fixed charge density from the insulator-thickness dependence of the threshold voltages of the MIS devices, we found a trend that the interface fixed charge density decreases with the decrease in the Al composition ratio, i.e., increase in the Ti composition ratio, which leads to shallow threshold voltages. This trend can be attributed to the large bonding energy of O-Ti in comparison with that of O-Al and to consequent possible suppression of interface oxygen donors. For an AlTiO gate insulator with an intermediate composition, the MIS field-effect transistors exhibit favorable device characteristics with high linearity of transconductance. These results indicate a possibility of interface charge engineering using AlTiO, in addition to energy gap engineering and dielectric constant engineering.

360 nW Gate-Driven Ultra-Low Voltage CMOS Linear Transconductor With 1 MHz Bandwidth and Wide Input Range

A low voltage linear transconductor is introduced. The circuit is a pseudo differential architecture that operates with ±0.2V supplies and uses 900nA total biasing current. It employs a floating battery technique to achieve low voltage operation. The transconductor has a 1MHz bandwidth. It exhibits a SNR = 72dB, SFDR = 42dB and THD = 0.83% for a 100mVpp 10kHz sinusoidal input signal. Moreover, stability is not affected by the capacitance of the signal source. The circuit has been validated with a prototype chip fabricated in a 130nm CMOS technology.

Design of a CMOS 65‐nm inductor‐less VCO for ISM applications in the VHF band

SummaryThis paper presents a design of a CMOS cross‐coupled voltage‐controlled oscillator (VCO) using active inductors (AIs) for wide‐band applications and can also be applied to various wireless technologies standards. The compatibility of this design to different wireless standards highlights its potential to be implemented at the core of the communication front end in the Internet of Things (IoT). The proposed AI design employs a gyrator‐C topology as the basic structure to generate an inductance. The VCO uses a cross‐coupled oscillator structure with a pair of varactors to sweep the frequency. Two extra capacitors, between the AIs and the outputs of the VCO core tank, are employed to enhance the performance of the phase noise and make the VCO work similarly to a linear transconductance (LiT) oscillator. Both the AIs and the VCO are designed in the TSMC 65‐nm CMOS technology, and the performance is analyzed using postsimulation results, as well as through measurements. The fundamental frequency spans from 140 to 463 MHz. Thus, the relative tuning range of this design is approximately 107%. The optimal phase noise of the design is around −97 dBc/Hz at 1‐MHz offset. Furthermore, it achieves an excellent figure of merit (FOM) around −163 dBc/Hz with a direct current (DC) power consumption less than 3 mW. The proposed design shows an advantage in phase noise and power consumption in comparison with previous active inductor VCO and ring VCO designs, respectively. The final layout occupies only 0.4 × 0.62 mm2 including the pads. The proposed AI‐VCO shows a compact size, linear tuning, low power consumption, and good phase noise performance.

A folded-cascode mixer for mixing-spur suppressions in a 2.4-to-5.8 GHz transmitter

This paper presents a folded-cascode mixer for an ISM band transmitter that translates the signals at the 2.4 GHz band to 5.8 GHz. Comparing to the conventional Gilbert cell mixer, our proposed folded-cascode mixer architecture with DC offset blocking, and transconductance linearization techniques can effectively suppress the LO feedthrough by 9 dB. The proposed mixer is designed in 0.11 μm CMOS and consumes 2.6 mA from a 1.2 V supply. The simulation results show that the mixer achieves an output power of 4.7 dBm, and all the emission spurs are well below −40dBc.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS

A new solution for an ultralow-voltage bulkdriven (BD) asynchronous delta-sigma modulator is described in this paper. While implemented in a standard 0.18-μm CMOS process from the Taiwan Semiconductor Manufacturing Company and supplied with VDD = 0.3 V, the circuit offers a 53.3-dB signal-to-noise and distortion ratio, which corresponds to 8.56-bit resolution. In addition, the total power consumption is 37 nW, the signal bandwidth is 62 Hz, and the resulting power efficiency is 0.79 pJ/conversion. The above-mentioned features have been achieved employing a highly linear transconductor and a hysteretic comparator based on nontailed BD differential pair.

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs

A power-efficient pipeline analog-to-digital converter (ADC) architecture employing a current-mode (CM) multiplying digital-to-analog converter (MDAC) is implemented in this paper. A linear operational transconductance amplifier (OTA), a current steering DAC, and a transimpedance amplifier (TIA) work together as an error amplifier to implement the first stage of the pipeline ADC. The high output impedance displayed by both OTA and MDAC allow us to maximize the power efficiency of the residue amplifier. Compared with a conventional switched-capacitor (SC) MDAC architecture, the proposed CM MDAC reduces the architecture’s power consumption. The fabricated pipeline ADC achieves a 61.3-dB/60.2-dB signal-to-noise and distortion ratio (SNDR) and a 76-dB/74-dB spurious-free dynamic range (SFDR) for a sinusoidal input of 4.15 and 97.9 MHz, respectively. The ADC’s power consumption when operating at 200 MS/s is 8.4 mW, and the conversion figure of merit (FoM) is a 44 fJ/conversion step. The prototype occupies an active area of 0.23 mm2 in a mainstream low-power 40-nm CMOS technology.

A new active resistor and its application to a CMOS transconductor

In this paper a new active resistor is proposed which is suitable for tunable linear voltage to current converters. The proposed resistor is composed of the main and auxiliary triode-mode transistors in which the resistance of auxiliary transistor adds to that of main transistor at a specific tune voltage. By this way the triode operation of both transistors is ensured throughout the tuning range. The proposed resistor is used in a tunable linear transconductor. The proposed transconductor which is implemented in 0.13 μm CMOS technology works with 1.2 V supply voltage and its power consumption changes between 682 and 980 μW. Simulation results show 20 dB improvement in THD of transconductor thanks to using proposed resistor rather than conventional one for input voltage amplitude of 1Vpp at 1 MHz. The transconductance can be tuned from 68 to 177.4 μA/V and the THD remains less than −55 dB for input voltage amplitudes up to 1.2Vpp and for the entire tuning range.

0.3-V Bulk-Driven Nanopower OTA-C Integrator in 0.18 µm CMOS

This short paper presents the experimental results for a 0.3-V fully differential OTA-C integrator, implemented in a standard n-well 0.18 µm CMOS technology from TSMC with chip area 350 × 100 µm. The integrator consists of an adaptively biased bulk-driven linear operational transconductance amplifier (OTA) and a low-distortion common-mode feedback circuit. The integrator can operate with supply voltages ranging from 0.3 to 0.5 V. For a 0.3-V version, its cutoff frequency can be tuned from 50 to 334 Hz for a 220 pF load capacitance. For a nominal biasing current, its power consumption is 50 nW and the dynamic range is 75 dB.

Analysis and design of highly linear Gm–TIA PGA with flat gain response

This paper analyzes high linearity Cherry–Hopper programmable-gain-amplifier (PGA), which is a cascade of linear transconductance (Gm) stage and transimpedance (TIA) stage. Basing on these analysis, reasons for gain peaking of Gm–TIA PGA are discussed. A Gm–TIA PGA with flat gain response and high power-efficiency is designed, and implemented in a 0.18 μm CMOS process. It draws 260-μA current from a supply of 1.8-V, while maintains a constant bandwidth of 24-MHz when driving a capacitive load of 2-pF. Flat gain response over the gain range is obtained, and the measured OIP3 reaches 19.5 dBm.

Influence of Fin Configuration on the Characteristics of AlGaN/GaN Fin-HEMTs

In this paper, AlGaN/GaN Fin-HEMTs with different fin configurations are theoretically and experimentally investigated. A simple physical-based threshold voltage model for AlGaN/GaN Fin-HEMTs is built for qualitative analysis. It is shown that the threshold voltage of AlGaN/GaN Fin-HEMTs depends on the width and height of the fin structure. The peak value and linearity of transconductance and current gain cutoff frequency are improved by reducing the fin length. It is also found that the linearity of transconductance is sensitive to the fin height, which can be attributed to the capacitance control from sidewalls.

Compact CMOS LiT VCO achieving 198.6 dBc/Hz FoM A

A compact CMOS linear transconductance (LiT) voltage-controlled oscillator (VCO) in 65 nm CMOS process is presented. The proposed LiT technique is realised using NP core without a choke inductor to reduce die area and avoid dual resonance problem. The measured output frequency of the proposed VCO shows 11.18–11.98 GHz and phase noise is −112.62 dBc/Hz at 1 MHz offset frequency. DC power consumption of the VCO core and the buffer is 5.86 and 6 mW, respectively. It achieves a high figure of merit normalised to the area of 198.6 dBc/Hz.

Wide digitally tunable lowpass filter for biomedical and wireless applications

A fully differential Gm-C lowpass filter for wireless and biomedical applications is introduced in this Letter. The proposed filter is based on a highly linear CMOS digital programmable operational transconductance amplifier (DPOTA).The filter consists of a parallel connection of three fourth-order Butterworth sections. Each section is optimised for a specific band of frequencies which can be tuned digitally. Switching between the different sections is achieved by controlling the corresponding DPOTAs' transconductance values, hence, this filter design eliminates the need for switches. Simulation results for a 90 nm CMOS technology are given. The third-order harmonic distortion (HD3) of the DPOTA remains below −60 dB up to 0.5 V differential input voltage at 1.2 V supply voltage. The proposed filter exhibits a wide cutoff frequency tuning range, from 100 Hz to 12 MHz, thus it covers many biomedical and wireless communication standards.

Low power and adjustable biomedical sensor interface system

In this paper a new sensor interface using current mode approach is presented for biomedical applications. The proposed sensor interface utilises a low-power current-mode comparator, an 8 bit current mode successive approximation analogue to digital converter (SA-ADC), an adaptable band-pass filter as well as a highly linear transconductance amplifier (Gm). The Gm and current mode SAR ADC are designed in a way to achieve minimum power consumption. The circuit is simulated in 0.18 μm CMOS technology with supply voltage of 1.8 V. At 400 KS/s sampling frequency, the total power consumption and total harmonic distortion of the system are obtained equal to 2.2 μW and 45.2 dB respectively. The simulation results demonstrate the effectiveness and superiority of the proposed circuit in comparison with the conventional circuits.

Hysteresis Bearingless Slice Motors with Homopolar Flux-biasing.

We present a new concept of bearingless slice motor that levitates and rotates a ring-shaped solid rotor. The rotor is made of a semi-hard magnetic material exhibiting magnetic hysteresis, such as D2 steel. The rotor is radially biased with a homopolar permanent-magnetic flux, on which the stator can superimpose 2-pole flux to generate suspension forces. By regulating the suspension forces based on position feedback, the two radial rotor degrees of freedom are actively stabilized. The two tilting degrees of freedom and the axial translation are passively stable due to the reluctance forces from the bias flux. In addition, the stator can generate a torque by superimposing 6- pole rotating flux, which drags the rotor via hysteresis coupling. This 6-pole flux does not generate radial forces in conjunction with the homopolar flux or 2-pole flux, and therefore the suspension force generation is in principle decoupled from the driving torque generation. We have developed a prototype system as a proof of concept. The stator has twelve teeth, each of which has a single phase winding that is individually driven by a linear transconductance power amplifier. The system has four reflective-type optical sensors to differentially measure the two radial degrees of freedom of the rotor. The suspension control loop is implemented such that the phase margin is 25 degrees at the cross-over frequency of 110 Hz. The prototype system can levitate the rotor and drive it up to about 1730 rpm. The maximum driving torque is about 2.7 mNm.