Linear Phase Detector Research Articles

A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC

Waveform digitization is an important research direction in high-energy physics experiments. Compared to analog-to-digital converter (ADC) solutions, switched capacitor arrays (SCAs) have the advantages of high sampling rate, low power consumption, and easy multichannel integration. However, the dead time of SCA is a limitation for high-hit-rate applications. To reduce the quantization time contributed by the on-chip Wilkinson ADC, a strategy of a high-speed less-bit coarse counter combined with multi-phase clock locking can be adopted. In this case, a high-precision PLL with multiple phases is needed. This paper presents the design and test of a 4-phase PLL for a 12-bit single-slope ramp ADC employed in our SCA ASIC in research. It contains a linear phase and frequency detector (PFD), a current steering charge pump (CP), a second order loop filter, a wideband voltage-controlled oscillator (VCO), VCO calibration, a band-locked detector, and a frequency divider (FD). The frequency tuning range is achieved from 1 GHz to 2 GHz. In addition, another output clock, supporting division by 1, 2, 4, or 8, can be used as a serial readout clock. The PLL has been designed and fabricated in 0.13 μm CMOS technology. The 1024-cycle jitter is approximately 0.013 periods. The area of the PLL core is 0.077 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the PLL core is 14.5 mW.

An approach for linear optical phase demodulation using a single photodetector.

In this paper, we propose and experimentally verify a phase-modulated radio-over-fiber (RoF) link capable of transmitting the radio frequency (RF) signal linearly. By executing the Kramers-Kronig (KK) algorithm at the receiver, the proposed link can accomplish linear optical phase demodulation with a single photodetector rather than a coherent receiver. In the 16-quadrature amplitude modulation (16-QAM) and 64-QAM microwave vector signal transmission experiments, measured error vector magnitudes (EVMs) are 4.14% and 4.38%, respectively, after 25-km fiber transmission, and the measured spurious-free dynamic range (SFDR) is 114.5 dB·Hz2/3, which shows a good performance in linearity.

A 6.0–11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique

A reference-less sub-baud-rate linear clock and data recovery with a frequency acquisition is proposed to operate from 6 to 11 Gb/s. The proposed frequency acquisition technique operating at a single differential quarter-rate clock and sharing the same phase detector achieves low power consumption. Fabricated in a 28-nm CMOS technology, the frequency detection (FD) logic and locked detector (LD) consume only 0.62 mW. Furthermore, the proposed sub-baud-rate linear phase detector with dead zone free guarantees the in-band recovered phase noise and needs no accuracy reference voltage threshold for phase locking. The proposed sub-baud-rate CDR consumes 8.66 mW, corresponding to power efficiency of 0.86 pJ/bit at 10 Gb/s.

Linear phase detector for detecting multiple leaks in water pipes

Acoustic signals measured at either side of a leak have been widely used for locating leaks in buried water distribution pipes. Conventional acoustic leak localization techniques (e.g, cross-correlation) may only pick up the strongest leak when multiple leaks exist in the same pipe. In this paper, a new method based on a linear phase detector has been proposed to address this issue for leak detection in water pipes. The linear phase detector utilizes the phase curve between the leak signals measured at two sides of the leaks. It involves an inverse optimization process that optimally identifies linear phase segments in the phase curve. Multiple leaks can be identified by these linear phase segments with different slopes which are correlated with the leak locations. Field investigations have been carried out on a water pipe which is a part of the water distribution system in a busy city area. The field experimental results validated the proposed method with two leaks close to each other being successfully detected.

Solving Phase Ambiguity in Interferometric Displacement Measurement With Millimeter-Wave FMCW Radar Sensors

The frequency-modulated continuous-wave (FMCW) radar sensor is subject to phase ambiguity in measuring large displacement of over half a wavelength, which is particularly severe in the millimeter-wave FMCW radar sensor due to its short wavelength. The state-of-the-art linear phase demodulation techniques were mostly developed for single tone quadrature continuous-wave (CW) radars such as the Modified differentiate and cross-multiply (MDACM) algorithm. This paper presents a novel linear interferometric displacement measurement technique which can synthesize the quadrature <inline-formula> <tex-math notation="LaTeX">${I}/{Q}$ </tex-math></inline-formula> signals across slow time from a single-channel FMCW radar. In this way, the linear phase demodulation technique developed for the CW radar can now be leveraged for the FMCW radar. The theoretical analysis and working principles are discussed. Exhaustive experiments are performed to validate the proposed technique. It is demonstrated that the displacement motions as large as 10 times of the wavelength can be precisely extracted from a single channel FMCW radar with micrometer accuracy and without any phase ambiguity.

Remote Michelson interferometric phase sensor based on dual-core fiber transmission and linear phase demodulation.

We present a remote Michelson interferometric phase sensor based on dual-core fiber transmission and linear phase demodulation. The former allows for synchronous transmission of both sensing signal and reference lights, enabling efficient suppression for the environmental disturbances along the transmission link and for the incoherent phase noise between the two lights. The latter is conducted by two optical phase-locked loops, one of which consists of a fiber stretcher that is used to eliminate the residual phase noises, thus stabilizing the operation point while the other relies on a phase modulator that is used to track the remote phase changes, thus achieving a highly linearized phase demodulation. A remote phase sensing over a 20 km fiber link with less than 3% nonlinear phase error over 3π range has been readily realized, corresponding to more than 10 times extension in a linear phase demodulation range. The proposed system shows great potential in the field of remote phase sensing for a variety of physical quantities.

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator

This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quarter-rate operation. Fabricated in a 40-nm CMOS process, the prototype achieves a bit efficiency of 0.46 pJ/bit at 32-Gb/s input data rate. The measured jitter tolerance (JTOL) at the bit error rate (BER) of < 10−12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz. The measured integrated jitter of the 4-GHz recovered clock is 352.6 fs.

Referenceless single‐loop CDR with a half‐rate linear PD and frequency acquisition technique

A referenceless single-loop clock and data recovery (CDR) circuit with a half-rate linear phase detector (PD) and an inherent frequency acquisition technique are introduced. Cycle-slip in the half-rate linear PD and its relationship with the frequency acquisition are described in detail. The single-loop CDR consists of a conventional phase-tracking loop and a frequency-tracking unit, referred to as the cycle-slip detector. The proposed CDR is fabricated in a 28 nm CMOS process and achieves a wide capture range of 2.6 Gb/s for a PRBS31 pattern. The RMS and peak-to-peak jitter of the recovered clock are and , respectively, at 8 Gb/s. The high frequency jitter tolerance is measured as . The CDR occupies and consumes 26 mW at 8 Gb/s from a 1.0 V supply.

Low-Power All-Digital Multiphase DLL Design Using a Scalable Phase-to-Digital Converter

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation are investigated. The digitally controlled shunt-capacitor inverter (SCI) delay cell leads to an extremely small design with the delay line being the only analog component, while the voltage controlled current-starved inverter (CSI) delay cell has a lower power consumption and less jitter. The proposed design procedure of the SCI based DLL allows fast simulation using Verilog based models since no analog low pass filter is required. Using the proposed modeling technique for the PDC, the behavior of the DLL can be estimated based on input clock jitter specifications. The SCI and CSI based multiphase DLL designs are fabricated in a 65nm CMOS process operated from a 1.2V supply. The proposed SCI based DLL occupies only 0.0048mm2 of active area and consumes 2.25mW at 2.5GHz input frequency with a 622.6MHz sample clock. The RMS jitter of the circuit is 1.2 ps and 1.4 ps for the DLL loop and the phase shifter loop, respectively. The RMS jitter is significantly reduced with the CSI based DLL to 0.86 ps and the power consumption of 2.64mW at 4GHz input frequency with a 996.1MHz sample clock provides an improved power efficiency compared to the SCI based DLL. As a trade-off, the area is increased to 0.0085mm2 due to the use of a $\Delta \Sigma $ modulator and an analog low pass filter.

A Novel Spectral-Efficient Coherent Radio-Over-Fiber Link With Linear Digital-Phase Demodulation

In this paper, a novel spectral-efficient coherent radio-over-fiber (RoF) link with linear digital phase demodulation is proposed and experimentally demonstrated. At the transmitter, to make an efficient use of the optical power and spectra, an intensity-modulated optical signal serving as the optical reference signal and a phase-modulated optical signal are polarization-multiplexed on a single optical carrier. At the receiver, the two optical signals are coherently detected with an optical local oscillator (OLO) and demodulated free of laser phase fluctuation through digital signal processing. Owing to simple and linear digital phase demodulation, an RF input signal is linearly demodulated from the optical phase without approximations and preconditions, which preserves the linearity of the phase-modulated RoF optical link from the transmitter end to the receiver end. The proposed scheme is experimentally verified by 25-km single-mode-fiber (SMF) transmission of two 16-QAM microwave vector signals at 2 GHz and 2.4 GHz, both with a symbol rate of 50 Msymbol/s. The transmission performance in term of error vector magnitude (EVM) is evaluated. Additionally, 25-km SMF transmission of the phase-modulated input signal with a spurious-free dynamic range (SFDR) of 112.8 dB·Hz2/3 is obtained.

Wideband OPLL photonic integrated circuit enabling ultrahigh dynamic range PM RF/photonic link

The RF/photonic link is the basic element of microwave photonics. Previous RF photonic links often rely on optical intensity modulation. The inherent modulation nonlinearity leads to inadequate spurious free dynamic range (SFDR) for many sought-after microwave photonic applications in radar. A new phase-modulated (PM) link with an optical phase-locked loop (OPLL) demodulator could afford a promising solution for the SFDR. However, the efficacy of the PM link approach remained unsubstantiated as previous OPLL implementations had too restricted of a bandwidth for realistic applications. Here, we present a new OPLL photonic integrated circuit (PIC) chip that offered quadrupled bandwidth enhancement over the state of the art. The OPLL PIC represents the first OPLL linear optical phase demodulator with sufficient bandwidth for realistic microwave photonic applications. With help of the OPLL PIC, a PM RF/photonic link demonstrated a record-breaking SFDR of ∼129.3 dB·Hz2/3 and a 3 dB SFDR bandwidth of ∼1 GHz. The combined SFDR and bandwidth performance amounts to around 1 order of magnitude improvement over the prior state of the art.

Self-referencing mW-scale detection of sub-ns optical phase modulation in acetylene at 1530 nm.

Application of the phase memory of acetylene (C2H2) vibrational-rotational transitions in the 1520-1540nm wavelength range for a self-referencing homodyne detection of a sub-nanosecond optical phase modulation is reported. In the proposed configuration the collinearly propagating coherent dipole radiation of the excited molecule acts like a phase-locked reference wave (local oscillator) that enables transformation of the initial phase modulation into the intensity one. This technique does not need high light intensity and can operate in a linear range of the medium optical absorption. The linear optical phase demodulation (i.e., transformation of the phase-to-amplitude light modulation) is interpreted as an introduction of an additional phase shift to the carrier frequency component of the modulated signal in the maximum of the dispersion curve of a narrow optical absorption peak. It has been experimentally demonstrated with the bulk 10cm long cuvette filled with low pressure (∼2 Torr) acetylene at room temperature. Effective demodulation of the milliwatt-scale incident laser wave of a single- and multi-mode structure is shown. As expected, the response to the fast (<1 ns) phase modulation was quadratic when the acetylene inhomogeneous Doppler-broadened (∼500 MHz) absorption line is excited in its center and was linearized by tuning at one of the absorption line sides. It is of a differentiating (high-pass) type with the cutoff frequency determined by the total spectral width of the utilized absorption line. Expected detection resolution is determined by the photon noise of the incident light intensity.

A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort

This paper describes a low-power reference-less 5.4-Gb/s clock and data recovery (CDR) circuit with a fully digital quarter-rate linear phase detector (QLPD) having an extended pulse width output. By using a fully digital circuit and merging XOR function with charge pump, the power efficiency and linearity of the phase detector are improved. The proposed QLPD responds correctly up to 0.75 UI of phase difference at 5.4 Gb/s. The CDR was designed to conform to Embedded DisplayPort (eDP) standard of the Video Electronics Standards Association (VESA). The proposed CDR circuit has been fabricated using a 40-nm CMOS technology. The jitter tolerance (JTOL) margin was measured at 0.75 UI, which is 20% higher than the eDP specification of 0.624 UI at the 20-MHz jitter frequency. BER was measured as less than 10−12 with a 27−1 pseudo random bit sequence (PRBS) pattern. The CDR consumes 12.99 mW, including a bandgap reference circuit and power efficiency achieving 2.41 pJ/bit at 5.4 Gb/s. The area of the proposed CDR is 0.13 mm2.

Design of All Digital Phase Locked Loop for Wireless Applications

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (fDATA) and the recovered clock frequency (fCLK) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of fDATA and fCLK is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations.

A 26-Gb/s 0.31-pJ/bit Receiver With Linear Sampling Phase Detector for Data and Edge Equalization

A source-synchronous receiver with a quarter-rate linear sampling phase detector (LSPD) using an embedded feed forward equalizer (FFE) and decision feedback equalizer (DFE) is proposed for chip-to-chip/module-to-module communication with medium channel loss. The quarter-rate LSPD is proposed to save power and avoid dithering jitter in a nonlinear bang-bang phase detector. To relax the timing constraint and improve the jitter performance of the recovered clock, a 1-tap FFE and a 1-tap DFE are applied to both the data path and the edge path so as to cancel the first and second post-cursors by reusing the linear samples. A charge-steering technique is adopted in the equalizer summer to minimize the power overhead. The receiver IC is fabricated in a 28-nm CMOS process and achieves error-free operation up to 26 Gb/s with a superior bit efficiency of 0.31 pJ/b while tolerating a 14-dB channel loss at 13 GHz.

Monolithically Integrated Virtual Balanced ACP-OPLL for PM RF Photonic Links

We present the analysis, design, fabrication, and measurement of the attenuating counter-propagating optical phase locked loop (ACP-OPLL) photonic integrated circuit with a virtual balanced device structure for high dynamic range RF photonic links. The virtual balanced design not only significantly reduces fabrication complexity, but also improves the optical loss performance. The virtual balanced ACP-OPLL demonstrated the best linear phase demodulation performance among the OPLL photonic integrated circuits.

A 1.62–5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques

We present a 1.62–5.4-Gb/s receiver for DisplayPort version 1.2a and propose an adaptive equalizer (EQ) with a peak-level comparison technique for eye measurement. A single comparator and an up/down unmatched-current charge pump are used to realize a simpler EQ architecture with low power dissipation. A referenceless frequency acquisition technique is also proposed. A time-to-digital converter-based pulsewidth detector supports the referenceless frequency acquisition within the range of 1.62–5.4 Gb/s. An XOR-gate-embedded charge pump and a half-rate linear phase detector were used to improve the jitter tolerance (JTOL) performance. The measured eye opening of the proposed EQ at 5.4 Gb/s was 0.68 UI with a −20-dB loss channel. The proposed receiver passed all the JTOL tests of the DisplayPort compliance specification version 1.2b. The power consumption of the receiver was 36.8 mW at 5.4 Gb/s. The receiver occupied a core area of 0.265 mm2 using 65-nm CMOS process technology.

Modified Sagnac Loop Coherent Phase Modulated RF Photonic Link With an ACP-OPLL

The first Sagnac loop coherent phase modulated RF photonic link employing an ACP-OPLL linear phase demodulator was presented. This structure demonstrated stable signal transmission over a 1-km long coherent RF photonic link. Except for optical loss of the long optical fiber, no penalties in the noise and linearity performance were observed.

On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors

Until now, it has been known that the full-rate linear and binary phase detectors (PDs) cannot detect the frequency difference between the received data and the recovered clock in clock and data recovery (CDR) loops. In this brief, we study the frequency characteristics of the full-rate linear and binary PDs and show that, unlike the binary PD, the linear PD has not only phase detection capability but also frequency detection capability intrinsically. According to our frequency-locked loop analysis, the locking trajectory of a referenceless CDR with only the full-rate linear PD in the single-loop architecture can be represented by using an exponential decay function with a single time constant. MATLAB Simulink simulations agree well with the predicted locking trajectory, which verifies that the full-rate linear PD has frequency detection capability.