A 26-Gb/s 0.31-pJ/bit Receiver With Linear Sampling Phase Detector for Data and Edge Equalization

Abstract

A source-synchronous receiver with a quarter-rate linear sampling phase detector (LSPD) using an embedded feed forward equalizer (FFE) and decision feedback equalizer (DFE) is proposed for chip-to-chip/module-to-module communication with medium channel loss. The quarter-rate LSPD is proposed to save power and avoid dithering jitter in a nonlinear bang-bang phase detector. To relax the timing constraint and improve the jitter performance of the recovered clock, a 1-tap FFE and a 1-tap DFE are applied to both the data path and the edge path so as to cancel the first and second post-cursors by reusing the linear samples. A charge-steering technique is adopted in the equalizer summer to minimize the power overhead. The receiver IC is fabricated in a 28-nm CMOS process and achieves error-free operation up to 26 Gb/s with a superior bit efficiency of 0.31 pJ/b while tolerating a 14-dB channel loss at 13 GHz.