Linear Low Noise Amplifier Research Articles

A mm‐wave LNA employing current re‐use and non‐linearity cancellation in 28 nm CMOS for automotive RADAR and 6G receivers

AbstractThis letter reports an 85 GHz low noise amplifier (LNA) employing derivative superposition based non‐linearity cancellation and a current re‐use topology. The LNA employs a two‐stage stacked architecture, each featuring neutralized differential pairs utilizing the same DC current. In derivative superposition, an auxiliary branch consisting of neutralized differential pairs cells is added in the LNA in parallel to stage 1 to ensure non‐linearity cancellation. Layout‐based capacitive neutralization is implemented to improve GMAX, resulting in simplified routing, reduced parasitics, and a more compact layout. The proposed LNA is fabricated in TSMC 28 nm CMOS process and achieves a peak gain of 8.4 dB at 84.2 GHz with a measured 3 dB bandwidth () from 79.4 to 92 GHz. The minimum measured noise figure is 12.8 dB. The LNA draws 34 mA of DC current from a 1.2 V supply. The highly linear LNA with IIP3 +6.5 dBm is tailored for automotive RADAR and 6G receivers.

Design of a Source Degenerated Cascode Stage Low Noise Amplifier for 5G Applications

Low Noise Amplifier (LNA) is the most critical part of a receiver front end in terms of the receiver performance. The performance tradeoff among input matching, noise figure, gain, and linearity are analyzed in detail. The LNA finds its application at Portable GPS Receiver, BLE, Zigbee, NFC, WiFi, Wireless Sensor Network, RFIC operating at 2.4GHz frequency. Millimeter wave communication is an evolving technology for bandwidth demanding 5G wireless application. A high gain and linear narrowband cascode Low Noise Amplifier (LNA) operating at 2.18GHz to 2.47GHz is proposed. To demonstrate design methodology, a narrow-band source degenerated cascode LNA is designed and simulated in a standard 90nm CMOS process to operate in the 2.4 GHZ band. The LNA achieves a voltage gain of 5.38dB, Noise figure of 4.1127dB, and from 3.2 V supply voltage. Proper input and output impedance matching have been performed to achieve the input return loss of -14 dB (S11) and output return loss of -19.72 dB (S22). Simulation study has been done using Cadence spectre.

A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third-order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2.

Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure

In this paper, a Low Noise Amplifier (LNA) with the current reused topology is proposed for wideband applications. To increase input impedance matching common source with inductive degeneration and RC shunt feedback structure is used. To extend the bandwidth, inductive series peaking technique is utilized. In the next stage, two parallel structure is hired to have a high voltage gain with low power consumption in addition to improve linearity. Also, by using the self-forward-body-bias (SFBB) technique, supply voltage is reduced and as a result power consumption is decreased further. The proposed LNA exhibits the high and flat gain of 14.7–15.4 ​dB, input return loss of less than −11 ​dB and noise figure range of 2.3–4.4 ​dB from 1 ​GHz up to 8 ​GHz. It consumes 5.4 ​mW from a 1.2 ​V power supply. The achieved IIP3 range for the proposed LNA is 0 ​dBm up to +2.7 ​dBm. The proposed LNA occupies 0.45 ​mm2 in 0.18-μm CMOS technology.

Power-Efficient CMOS Cellular RF Receivers for Carrier Aggregation According to RF Front-End Configuration

This article presents power-efficient radio frequency (RF) receiver designs, particularly for advanced long-term evolution cellular applications. The two proposed single-ended receiver architectures can fully support multiple-channel RF signals in advanced carrier aggregation (CA) scenarios with maximum design flexibility depending on the RF front-end module configuration and target applications. Two different low-noise amplifier (LNA) topologies are employed in receivers to achieve different bandwidth handling capabilities and linearity requirements. The first receiver architecture utilizes narrowband LNAs with a current-reusing technique using a 28-nm low-power complementary metal-oxide-semiconductor (CMOS) technology. The proposed receiver with this single-ended narrowband LNA can handle up to three carrier components (CCs) CA. The second receiver architecture shows wideband characteristics and employs current-efficient and high linear wideband LNAs. This proposed design can support up to five CC CA and is implemented in a 14-nm Fin field-effect-transistor CMOS technology. Moreover, frequency-band switchable transformers are utilized in both designs to realize size-efficient receivers. Both proposed receivers operate at a frequency ranging from 0.6 to 2.7 GHz. The implemented narrowband and wideband receivers have conversion gains exceeding 70 and 62 dB, and achieve noise figures of less than 3.5 and 5 dB during all CA scenarios, respectively. The proposed receivers operate at a nominal supply of 1.2 and 1.0 V for 28 and 14-nm CMOS technologies, respectively.

A Wideband Differential Linear Low-Noise Transconductance Amplifier With Active-Combiner Feedback in Complementary MGTR Configurations

A wideband differential linear low-noise transconductance amplifier (LNTA) is proposed for SAW-less applications. An active combiner provides a dual-loop feedback for wideband matching with power efficiency. Operating as an auxiliary common source (CS) stage, complementary multi-gated transistor (MGTR) configurations are employed to compensate for the second- and third-order nonlinearity of the main CS stage, improving small-signal linearity. Large-signal linearity is also enhanced due to Class AB configurations. Additionally, the push-pull operation of the main CS stage and the auxiliary CS stage preserves good large-signal input matching performance. Implemented in a 0.18-μm CMOS process, the measured LNTA chip provides a minimum noise figure (NF) of 2.5 dB, and a maximum transconductance value of 76.7 mS from 0.1 to 3.1 GHz. On average, an input 1-dB compression point (IP1 dB) of 2.3 dBm and an input third-order intercept point (IIP3) of 17.8 dBm are obtained, respectively. The blocker NF is 4.0 dB under a 0 dBm blocker injection while the S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> <; -10 dB is maintained even with the blocker input of -3.1 dBm. The LNTA core only draws 13.3 mA from a 1.8 V supply.

Fully Integrated Tunable Q Enhanced Linear Low Noise Amplifier for Wireless Receivers

This paper presents the design of a fully-integrated tunable Q-enhanced LNA resonator filter designed to tune the circuit center frequency and quality factor Q. The proposed circuit achieves a 600 MHz 3dB bandwidth tunable center frequency at 2.4 GHz with a 5.5 dB Quality Factor Q tuning range. The proposed circuit utilize a distortion transistor compensator to improve linearity of the circuit. The results show an 18 dBc of third order intermodulation IM3 cancellation. The overall proposed circuit peak gain is 16.5 dB and the minimum NF is 0.94 dB at 2.4 GHz frequency with power consumption of 5.2 mA.

Highly linear wide band low noise amplifiers: A literature review (2010–2018)

Wideband (WB) CMOS low noise amplifier (LNA) design requires linearity consideration for better performance across the entire band because the increase in the number of interferers put severe constraints on system linearity requirements. In this paper, a literature review is presented within academic papers published with good linearity results on WB LNA between 2010 and 2018. Results of sample LNA designs are discussed with emphasis on bandwidth, noise figure (NF), gain and matching tradeoffs. This review provides useful insights on linearization techniques, the trade-offs consideration between the main parameters and also aids the creation of new ideas in this field. In addition, the designed LNAs have been compared with considering a new overall factor.

A 0.1–2.75 GHz high-linear low-noise transconductance amplifier for high-performance multi-standard wireless applications

The frequency bands below 3 GHz are occupied by various wireless applications. The overcrowding of many applications in these bands is the primary source of distortion in the wireless system. To combat distortion in the system, the radio frequency (RF) blocks must satisfy the linearity requirements of the application. Hence, in this paper, a high linear wideband low noise amplifier (LNA) stage is proposed for RF front-end. The LNA uses the combination of common-gate (CG) and common-source (CS) stages for cancelling the noise and distortion of the input matching CG stage. The CS stage exploits complementary derivative superposition (CDS) for linearity improvement, and cross-coupled local feedback network is employed for noise cancellation at the output. The LNA stage is designed using UMC 180 nm CMOS process technology and post-layout characterizations are carried out using Cadence SpectreRF circuit simulator. Also, the process corner, voltage, and temperature (PVT) variation analysis and Monte-Carlo simulations for mismatch analysis are carried out to verify the reliability of the LNA. The designed LNA has an input referred third-order intercept point (IIP3) of 8.85 dBm. The proposed LNA has a maximum gain of 23.96 dB and minimum noise figure (NF) of 1.4 dB with a total current consumption of 3.1 mA from a 1.8 V supply.

A Highly Linear Low-Noise Transimpedance Amplifier for Indoor Fiber-Wireless Remote Antenna Units

This article presents an optimized design of a low-noise transimpedance amplifier (TIA) with high linearity for use in the downlink receiver of a remote antenna unit (RAU). The aim of this design is to be used in a cost-effective indoor distributed antenna system (DAS) for WLAN transmission using a mixed fiber-wireless system. The circuit topology consists of a fully differential shunt–shunt feedback TIA with digitally programmable transimpedance. An open-loop gain compensation technique is used to maintain stability and constant bandwidth (BW). The TIA has been fabricated in 65 nm CMOS technology with a 1.2 V voltage supply. The total power consumption of the TIA is 6 mW. A complete electrical and optical characterization with a 1550 nm PIN photodiode has been performed to demonstrate the reliable 54 Mb/s 802.11a WLAN transmission achieved with an error vector magnitude (EVM) lower than 3% for a 20 dB optical input range.

A Highly Linear Dual-Gain CMOS Low-Noise Amplifier for &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$X$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Band

A highly linear X-band low-noise amplifier (LNA) is proposed and implemented in a standard 0.18- $\mu \text{m}$ CMOS technology. The LNA features both high- and low-gain operation modes. In its normal high-gain mode, the LNA shows a small-signal gain of 13.6 dB with an IIP3 of +9.5 dBm and a noise figure of 4.7 dB. The two-stage amplifier draws 90 mA from the 3.3-V power supply to achieve +14.8 dBm output P1dB (+2.2 dBm input P1dB). In the low-gain mode, the gain is reduced by about 10 dB to further enhance the linearity and to accommodate very large blockers. Accordingly, the input P1dB is enhanced to +13.7 dBm while the noise figure is increased by 8.1 dB. A technique is also introduced to maintain the input matching when the LNA is switched to operate in the low-gain mode.

A high linearity low-noise amplifier in 0.25 μm BiCMOS Qubic4x for GSM application

ABSTRACTIn this paper, a low-noise amplifier (LNA) in 0.25 μm BiCMOS Qubic4x technology for Global System for Mobile communications (GSM) application is presented. The LNA uses inductive source degeneration to achieve noise and power gain matching simultaneously and parallel RC feedback to improve linearity. The LNA provides a forward gain (S21) of 10.3 dB with noise figure (NF) of 1.5 dB while drawing 50.6 mW power from a 1.6 V voltage supply. The simulated 1-dB compression point is 0 dBm at 942 MHz. The simulations are done in cadence virtuoso Spectre RF using 0.25 μm BiCMOS Qubic4x technology.

Highly Linear High-Frequency Low-Noise Amplifier Design at ISM Band

A highly linear high-frequency low-noise amplifier is one of the important components in telecommunication receivers. The purpose of making such amplifiers is to amplify received signal from transmitter (antenna) at an acceptable level. A narrow band highly linear low-noise amplifier was studied and designed in this paper. A BFP720 bipolar transistor from Infineon Company associated with ADS software was used. Low-noise amplifier was initially designed and simulated and its results were obtained. Lumped elements of inductor and capacitor were used in the design of input and output matching network of this circuit, and two amplifier circuits were then designed and some techniques and methods proposed to improve its performance.

A Low-Energy Machine-Learning Classifier Based on Clocked Comparators for Direct Inference on Analog Sensors

This paper presents a system, where clocked comparators consuming only $CV^{2}$ energy directly derive classification decisions from analog sensor signals, thereby replacing instrumentation amplifiers, ADCs, and digital MACs, as typically required. A machine-learning algorithm for training the classifier is presented, which enables circuit non-idealities as well as severe energy/area scaling in analog circuits to be overcome. Furthermore, a noise model of the system is presented and experimentally verified, providing a means to predict and optimize classification error probability in a given application. The noise model shows that superior noise efficiency is achieved by the comparator-based system compared with a system based on linear low-noise amplifiers. A prototype in 130-nm CMOS performs image recognition of handwritten numerical digits, by taking raw analog pixels as the inputs. Due to pin limitations on the chip, the images with $28\times 28=784$ pixels are resized and downsampled to give 47 pixel features, yielding an accuracy of 90% for an ideal ten-way classification system (MATLAB simulated). The prototype comparator-based system achieves equivalent performance with a total energy of 543 pJ per ten-way classification at a rate up to 1.3 M images per second, representing $33\times $ lower energy than an ADC/digital-MAC system.

A linear ultra wide band low noise amplifier using pre-distortion technique

This paper presents an Ultra Wide-Band (UWB) high linear low noise amplifier. The linearity of Common Gate (CG) structure is improved based on pre-distortion technique. An auxiliary transistor is used at the input to sink the nonlinear terms of source current, resulting linearity improvement. Furthermore, an inductor is used in the gate of the main amplifying transistor, which efficiently improves gain, input matching and noise performance at higher frequencies. Detailed mathematical analysis show the effectiveness of both linearity improvement and bandwidth extension techniques. Post-layout simulation results of the proposed LNA in TSMC 0.18µm RF-CMOS process show a gain of 13.7dB with −3dB bandwidth of 0.8–10.4GHz and minimum noise figure (NF) of 3dB. Input Third Intercept Point (IIP3) of 10.3–13dBm is achieved which shows 8dB improvement compared to conventional common gate structure. The core circuit occupies an area of 0.19mm2 including bond pads, while consuming 4mA from a 1.8-V supply.

Critical Current Spread and Thermal Noise in Bi-SQUID Cells and Arrays

We report on the detailed analysis of thermal noise, critical current spread, and parasitic elements influences on the bi-SQUID voltage response and its linearity. These results together with the results of our previous studies serve as a useful guidance in designing high-performance bi-SQUIDs and bi-SQUID arrays implemented in low-temperature superconductor or high-temperature superconductor for many applications such as linear low-noise amplifiers and high-sensitivity antennas.

Wideband highly linear LNA using modified cascode for simultaneous input and noise matching technique

ABSTRACTIn this letter, a highly linear low‐noise amplifier (LNA) MMIC configured by a modified cascode structure with the operation band from 1.8 GHz to 2.8 GHz is proposed. The modified cascode structure adopts inductive degeneration and an additional transistor used for linearity enhancement and simultaneous input and noise matching. Also, the resistive feedback at the input and inductive peaking at the output are applied to ensure the stability over the wideband operation. The proposed LNA MMIC was implemented by 0.5μm GaAs pHEMT process and showed the measured input third‐order intercept point (IIP3) of 15.5 ± 1.3 dBm, gain of 16.3 ± 2.2 dB, output P1‐dB of 16.7 ± 0.3 dBm and noise figure (NF) of 1 ± 0.2 dB from 1.8 GHz to 2.8 GHz . © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:15–17, 2017

Linearity improvement of gm-boosted common gate LNA: Analysis to design

This paper proposes a highly linear low noise amplifier (LNA) for ultra-wideband applications. It focuses on linearization of the basic active gm-boosted common gate (CG) LNA circuit by exploring the nonlinearity coefficients using the generalized nonlinearity model. Mathematical analysis shows that in active gm-boosted CG LNA, the third input intercept point (IIP3) of LNA depends on interaction between main and auxiliary amplifiers. The multiple gated transistor (MGTR) technique, which was previously developed, is applied to an active gm-boosted CG amplifier based on linearity analysis. Also an improved shunt peaking bandwidth (BW) extension technique is proposed in this paper that extends the flat BW up to 200%. Post-layout simulation results of the proposed LNA circuit in a 180nm RF CMOS process show +11dBm of IIP3 that indicates 12dB improvement comparing with conventional structures. The proposed wideband LNA has a voltage gain of 16dB,−3dB bandwidth from 1GHz to 10.3GHz, and minimum noise figure (NF) of 4.1dB. The simulated S11 is better than −10dB in whole frequency range while the LNA core draws 6mA from a single 1.8V DC voltage supply.

A Highly Linear Low Noise Amplifier With Wide Range Derivative Superposition Method

This letter presents an L-band highly linear differential low noise amplifier (LNA) in a standard 90-nm CMOS process. A wide range derivative superposition technique is proposed to maximize the third-order intercept point (IP3), and at the same time, minimize the third-order intermodulation distortion (IMD3) over a wide input power range. The LNA chip achieves a measured OIP3 of $+33.7~{\rm dBm}$ and IMD3 of $-65~{\rm dBc}$ with $-15~{\rm dBm}$ input power. The measured peak gain and minimum noise figure are 15.4 dB and 1.36 dB at 1.27 GHz, respectively. The LNA chip consumes 40 mA from a 3.3-V supply.

A 130 nm wideband fully differential linear low noise amplifier

In this paper, a wide-band fully differential linear low noise amplifier (LNA) in a standard 130nm CMOS process is presented. The LNA utilizes Active Post Distortion (APD) as a voltage combiner that prepares a linear transconductance for enabling harmonic cancellation, which can also mitigate the impedance matching device noise. The impedance matching device is connected to the output transistors to ensure the harmonic cancellation at output node while preserving NF and input return loss at input node. This harmonic cancelation is also APD that guarantees an IIP2 and IIP3 of about 26dBm and 4dBm respectively at output node. Operating in a wide bandwidth of about 1.5GHz from 3.5 to 5GHz, the LNA obtains a maximum power gain (S21) of about 14dB, input reverse isolation (S11) and NF of less than -15dB and 3.9dB respectively. From a 1V power supply it dissipates about 21mW and occupies 0.557×0.567mm2 of chip area.