Linear Field-effect Mobility Research Articles

A Short-Channel TFT of Amorphous In–Ga–Zn–O Semiconductor Pixel Structure With Advanced Five-Mask Process

We propose a new five-mask etch-stopper amorphous In-Ga-Zn-O semiconductor pixel structure for a high-resolution advanced-high-performance in-plane-switching (AH-IPS) display device. A short-channel length (under 5 μm) thin-film transistor (TFT) was successfully fabricated using a selfaligned damage preventing layer. The linear field effect mobility of the 4-μm channel length TFT was 10.4 cm 2 /V · s. Using the proposed structure, we successfully fabricated a 9.7-in AH-IPS quad-extended graphics array liquid-crystal displays panel.

High-Performance Transparent AZO TFTs Fabricated on Glass Substrate

High-performance transparent low-temperature top-gate type aluminum doped zinc oxide (AZO) thin-film transistors (TFTs) (W/L=100 or 10 μm) are successfully fabricated on glass substrate. All the process temperature is below 100°C. For VG=-2 to 5 V, the TFTs using sputtering deposit AZO layer at room temperature as channel layer exhibits excellent properties, such as a saturation mobility μs of 285 cm2/V·s, a linear field effect mobility μl of 143 cm2/V·s, a threshold voltage Vth of 0.9 V, a steep subthreshold swing of 108 mV/decade, a low off-state current value Ioff of 5×10-13 A, a high ON/OFF ratio of 2×109 and a high transmittance of 82.5%. The results highlight that excellent device performance can be realized in AZO TFTs. Note that this is the best performance of AZO TFT ever reported.

Record Mobility in Transparent p-Type Tin Monoxide Films and Devices by Phase Engineering

Here, we report the fabrication of nanoscale (15 nm) fully transparent p-type SnO thin film transistors (TFT) at temperatures as low as 180 °C with record device performance. Specifically, by carefully controlling the process conditions, we have developed SnO thin films with a Hall mobility of 18.71 cm(2) V(-1) s(-1) and fabricated TFT devices with a linear field-effect mobility of 6.75 cm(2) V(-1) s(-1) and 5.87 cm(2) V(-1) s(-1) on transparent rigid and translucent flexible substrates, respectively. These values of mobility are the highest reported to date for any p-type oxide processed at this low temperature. We further demonstrate that this high mobility is realized by careful phase engineering. Specifically, we show that phase-pure SnO is not necessarily the highest mobility phase; instead, well-controlled amounts of residual metallic tin are shown to substantially increase the hole mobility. A detailed phase stability map for physical vapor deposition of nanoscale SnO is constructed for the first time for this p-type oxide.

Amorphous In–Ga–Zn–O Dual-Gate TFTs: Current–Voltage Characteristics and Electrical Stress Instabilities

We studied the electrical characteristics and electrical stress instabilities of amorphous In-Ga-Zn-O (-IGZO) dual-gate thin-film-transistors (DG TFTs). A threshold voltage of the bottom-gate (BG)-driven -IGZO DG TFTs showed a linear dependence on the top-gate (TG) voltage. The slope of this dependence is associated with the ratio of the TG to BG insulator capacitance. The BG-driven DG TFT showed linear field-effect mobility comparable to that of a single-gate (SG) TFT without the TG electrode and a smaller saturation field-effect mobility and a larger subthreshold swing in comparison to the SG TFT. These characteristics were explained by the BG-driven DG TFT model formulated by taking the TG bias effect into account. The TG interface showed worse stability under an electric bias stress in comparison to the BG interface. It was also found that a negative voltage applied to the TG improved the stability of the DG TFT under a constant-current stress. These observations suggest that the BG-driven -IGZO DG TFTs with the appropriate negative TG voltage applied can simultaneously show both normally off characteristics and higher stability than the SG TFTs.

High performance solution-deposited amorphous indium gallium zinc oxide thin film transistors by oxygen plasma treatment

Solution-deposited amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with high performance were fabricated using O2-plasma treatment of the films prior to high temperature annealing. The O2-plasma treatment resulted in a decrease in oxygen vacancy and residual hydrocarbon concentration in the a-IGZO films, as well as an improvement in the dielectric/channel interfacial roughness. As a result, the TFTs with O2-plasma treated a-IGZO channel layers showed three times higher linear field-effect mobility compared to the untreated a-IGZO over a range of processing temperatures. The O2-plasma treatment effectively reduces the required processing temperature of solution-deposited a-IGZO films to achieve the required performance.

Reduced contact resistance in solution-processed phenylenevinylene-based copolymer thin-film transistors using annealing-induced morphological variation

A significant (about 10-fold) reduction in contact resistance in top-contact poly[divinyl-bis(hexyloxy)benzene-alt-diketopyrrolopyrrole] thin-film transistors was realized by changing the microscopic morphology of Au/polymer interface through thermal annealing. An enhancement of roughness was caused by the variation of molecular stacking, as confirmed by x-ray diffraction spectra. The influences of roughness variation on the mobility-dependent contact resistances were compared, and a more than 10-fold increase in linear field-effect mobility was obtained in annealed devices, approaching 10−3 cm2 V−1 s−1. Further analysis showed that the increased density of local states and better bulk transport near the contact interface, which resulted from the enhanced surface roughness, should be responsible for this improvement.

Zinc concentration dependence study of solution processed amorphous indium gallium zinc oxide thin film transistors using high-k dielectric

The effects of zinc concentration on the performance of solution processed amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) have been investigated using high-k aluminum titanium oxide as gate dielectric. The x-ray diffraction results confirmed that all the IGZO channel layers are amorphous. The performance of a-IGZO TFTs were investigated in the linear regime operation. Highest linear field-effect mobility of 5.8 cm2/V s with an Ion/Ioff ratio of 6×107 and subthreshold swing of 0.28 V/dec were obtained for the a-IGZO (311) TFTs. The obtained performance of the a-IGZO TFTs is very promising for low-voltage display applications.

Influence of the deposition temperature on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si:H TFT) have been fabricated at three different deposition temperatures (150, 200 and 250 °C) for the μc-Si layer. We found that the linear field effect mobility increases from 0.1 to 0.44 cm 2/V s by decreasing the temperature from 250 °C to 150 °C, and that the leakage current of TFTs with μc-Si deposited at 150 °C is lower than that of μc-Si:H deposited at 250 °C. Moreover, there is no influence of the deposition temperature on the stability of μc-Si:H TFTs. The improvement of the electrical characteristics at lower deposition temperatures is discussed in terms of a lower concentration of donor active oxygen atoms at lower temperature.

In Situ Analysis of Hole Injection Barrier of O[sub 2] Plasma-Treated Au with Pentacene Using Photoemission Spectroscopy

Pentacene was in situ deposited on both bare-Au and O 2 plasma-treated Au (O 2 -Au). The band structure at the interface of Au with pentacene was quantitatively determined using ultraviolet photoelectron spectroscopy. The work function of Au increased from 4.65 to 5.28 eV as the Au surface was treated with O 2 plasma. The corresponding interface dipoles were -0.30 eV for bare Au and -0.71 eV for O 2 -Au, respectively. Thus the hole injection barrier at the interface reduced from 0.45 to 0.15 eV by the O 2 plasma before the deposition of pentacene, leading to an increase of the linear field-effect mobility of thin-film transistors.

Enhancement of hole injection in pentacene organic thin-film transistor of O2 plasma-treated Au electrodes

The effect of oxygen plasma treatment on enhancement of hole mobility was demonstrated using pentacene organic thin-film transistors (OTFTs) with bottom-contact Au electrodes. Linear field-effect mobility increased from 3.2×10−2to7.4×10−2cm2∕Vs as the Au electrodes were treated with O2 plasma. Secondary electron emission spectra revealed that the work function of oxygen plasma-treated Au is 0.5eV higher than that of untreated Au. This led to a reduced hole injection barrier at the interface of Au with pentacene, increasing the field-effect mobility of OTFTs.

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1×10/sup -14/ A/μm when V/sub d/ equals -0.1 V.

High-performance poly-Si TFTs on plastic substrates using a nano-structured separation layer approach

We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm/sup 2//V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A//spl mu/m-channel-width at V/sub ds/=-0.1 V, sub-V/sub t/ swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V.

Pentacene TFT with improved linear region characteristics using chemically modified source and drain electrodes

We have fabricated pentacene active layer organic thin film transistors (OTFTs) using chemically-modified source and drain contacts with improved contact and linear region characteristics. OTFTs fabricated on heavily doped, thermally oxidized single-crystal silicon substrates have linear field-effect mobility greater than 0.5 cm/sup 2//V-s at a drain-source voltage of -0.1 V, on/off current ratio greater than 10/sup 7/, and subthreshold slope as low as 0.7 V/decade.

Fabrication of microcrystalline silicon TFTs using a high-density plasma approach

N-channel microcrystalline silicon (mc-Si) thin film transistors (TFTs) were fabricated using a high density plasma (HDP) approach. An electron cyclotron resonance (ECR) plasma source was employed to deposit all of the thin film materials needed for the transistor; that is, intrinsic mc-Si, n-type mc-Si, and dielectric silicon dioxide were grown with the ECR high density plasmas and the deposition rates for these films were in the range of 120-150 /spl Aring//min. The substrate temperatures during these depositions were maintained below 285/spl deg/C. To complete the fabrication of these TFTs, we used only two masks with one alignment. After 1 h annealing under forming gas atmosphere, the mc-Si TFTs perform with linear field effect mobility of 12 cm/sup 2//V-s, on/off ratio of 10/sup 6/, subthreshold swing of 0.3 V/decade, off-current of 4/spl times/10/sup -13/ A//spl mu/m and threshold voltage of 5 V.

Thin-film transistors in polycrystalline silicon by blanket and local source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625/spl deg/C or 1000/spl deg/C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600/spl deg/C, have a linear field-effect mobility of /spl sim/35 cm/sup 2//Vs and an ON/OFF current ratio of /spl sim/10/sup 6/, and TFTs with a maximum process temperature of 1000/spl deg/C, have a linear field-effect mobility of /spl sim/100 cm/sup 2//Vs and an ON/OFF current ratio of /spl sim/10/sup 7/. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600/spl deg/C showed a nearly twofold improvement in mobility (72 versus 37 cm/sup 2//Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current.