Linear Feedback Shift Register Research Articles

Design and Analysis of High Performance FinFET-Based Linear Feedback Shift Register for Cryptography Applications

Nowadays, all the elements of our surrounding is occupied by electronics. Electronics occupies major role on our day today life. Electronics device integration on a single chip enhances performance in terms of speed, low-power circuits, and area. Integration of VLSI provides better scalability and reliability. This research paper focused on the implementation of Linear feedback shift registers (LFSR) using FinFET techniques at the layout level for various applications, including cryptography. FinFETs are highlighted as a replacement for CMOS technology, offering advantages such as improved performance in terms of speed, low-power circuits, and area. Linear feedback shift registers are commonly used in digital systems and cryptography for generating pseudo-random sequences. The use of FinFET technology in the layout level suggests an interest in exploring advanced semiconductor technologies to enhance the performance of these circuits. The paper appears to cover different design methods of LFSRs, which could include aspects like circuit optimization, power efficiency, and reliability. The integration of electronics on a single chip, particularly with FinFET technology, is noted for its potential to provide better scalability and reliability. The first architecture is created using bulk CMOS techniques; whereas the second is constructed using two fin FinFET LFSRs. Using the Microwind designing tool, the third technique is developed with a 3-fin FinFET LFSR. It provides a solution for a novel FinFET architecture that implements LFSR. When comparing CMOS and FinFET circuit designs for LFSR, the latter achieves superior performance in terms of area and power efficiency. An analysis is conducted on the design techniques and performance of CMOS LFSR, 2 fin FinFET based LFSR, and 3 fin FinFET. According to the experimental findings, the CMOS-based LFSR uses 1.243 mW of power; the FinFET-based LFSR uses 90.47 μW, and the two fin FinFET LFRS uses 0.254 mW.

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters.

Design and Implementation of 32 Bit Linear Feedback Shift Register using FPGA

Abstract: Shift register is a common device for generating signals and sequences. Usually register is the combination of flipflops.The shift register is of two types which are: linear and nonlinear. Various sequences including pseudorandom codes are generated by linear and nonlinear feedback shift registers, respectively. Linear feedback shift register (LFSR) is composed of dynamic or static master-slave flip-flop. Its characteristics are usually characterized by a characteristic polynomial. The twoinput XOR gate is used to calculate the characteristic polynomial of the maximum or near maximum length of the feedback function without rectifying the register.

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

Design of a New Neuro-Generator with a Neuronal Module to Produce Pseudorandom and Perfectly Pseudorandom Sequences

This paper presents the design of a new neuro-generator of pseudorandom number type PRNG Pseudorandom Number Generator, which produces complex sequences with an adequate bit distribution. The circuit is connected to a neuronal module with six impulse neurons with different behaviors: spike frequency adaptation, phasic spiking, mixed mode, phasic bursting, tonic bursting and tonic spiking. This module aims to generate a non-periodic signal that becomes the clock signal for one of the LFSRs Linear Feedback Shift Register that the neuro-generator has. To verify its correct operation, the neuro-generator was subjected to a series of tests where the frequencies of the impulse neurons were modified. This modification allows the generation of a greater number of pulses at the output of the neuronal module, to obtain sequences with different characteristics that pass different NIST statistical tests (National Institute of Standards and Technology of U.S.). The results show that the new neuro-generator maintains pseudo-randomness in the sequences obtained with different frequencies and it can be implemented on a reconfigurable FPGA Field Programmable Gate Array Virtex 7 xc7vx485t-2ffg1761 device. Therefore, it can be used for applications such as biological systems.

A simultaneous area, delay and leakage current reduction method for Linear Feedback Shift Register (LFSR) using pulsed latches and DTMOS transistors

In digital circuits, the shift registers are the significant elements having the ability of storing and transmitting the data in sequential manner.The linear feedback shift register (LFSR) uses large number of flips-flops that consumes maximum amount of power. To overcome this issue, this research work concentrates on the design of LFSR for the area efficient, power reduction, minimization of delay and leakage current. By replacing the d-flip-flop with the bi-enabled pulsed latch to reduce the power consumption and delay of the proposed LFSR design. For the minimization of area, leakage current and delay, the hybrid body bias generator with dynamic threshold MOS (BBG-DTMOS) is used. Moreover, the pulsed clock signal is generated in the digital circuit with the aid of hybrid BBG-DTMOS technique. The proposed LFSR design is implemented in the tanner EDA tool with the available CMOS model libraries. Based on the implementation result, the proposed LFSR area is 1824 μm2and its power consumption is 172μW at a 100 MHz clock frequency withVDD=5V. Furthermore, having the better performance in different corners of the method, reduces the propagation delay and leakage current in the digital circuit. The proposed LFSR design is compared with some of the shift registers such as unidirectional and bidirectional shift registers. The existing clock pulse generator such as conventional, delayed clock pulse, TIMBER logic, PTL-AND logic and multiplexer based clock pulse generator (MCPG) are compared with the proposed BBG-DTMOS technique.

FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional–integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed.

Analysis of linear feedback shift registers and chaos-based techniques for image encryption

ABSTRACT Image encryption is not new. Several different encryption algorithms have been used. Some of the algorithms are based on random sequences generated using chao systems and DNA sequencing and others are based on compression. Still, others are based on Linear Feedback Shift Registers. This paper focuses on research solutions for securing digital images including medical images. Medical images are important and are generally regarded as sensitive in nature. In this research paper, higher order linear feedback shift registers are developed using combination of lower order LFSRs by suitable clocking and the ciphers generated are utilized to encrypt digital images. Our analysis involves using suitable metrics to compare the chaos-based and LFSR-based stream ciphers for image encryption.

Design of Universal Code Generator for Multi-Constellation Multi-Frequency GNSS Receiver

A multi-constellation, multi-frequency Global Navigation Satellite System (GNSS) receiver is capable of simultaneously receiving signals from multiple satellite constellations across various frequency bands. This allows for increased observations, thereby enhancing navigation accuracy, continuity, effectiveness, and reliability. The spread spectrum code structures used in satellite navigation signals differ among systems. Compatible code generators are employed in multi-constellation, multi-frequency GNSS receivers to support tasks such as signal acquisition and tracking. There are three main types of spread spectrum code structures: Linear Feedback Shift Register (LFSR), Legendre sequences, and Memory codes. The Indian Regional Navigation Satellite System (IRNSS) released the L1-SPS (Standard Positioning Service) signal format in August 2023, which utilizes the Interleaved Z4-linear ranging code (IZ4 code) as its spread spectrum code. Currently, there is no universal code generator design compatible with the IZ4 code. In this paper, a proposed universal code generator is based on the hardware structure of the IRNSS IZ4 code generator. It achieves compatibility with all LFSR-based spread spectrum codes and enables parallel generation of multiple sets of GNSS signal spread spectrum codes, thereby improving hardware utilization efficiency. The proposed structure is implemented and validated using FPGA design, and resource consumption is provided as part of the validation results.

Enhancing Data Protection through Advanced Encryption or Improving Data Security with Advanced Encryption

The protection of information content is becoming a key concern with the recent exponential growth of digital data interchange over computer networks. Numerous security vulnerabilities can readily jeopardize the information sent over a network. An enhanced modification for the Advanced Encryption Standard (AES) algorithm is proposed and implemented using an additional key that generated using a linear feedback shift register (LFSR), which provides an efficient technique to pseudo random number generation and also reduces the number of rounds. Cryptography plays a crucial role in ensuring the security of digital data transmission over these unsafe networks. When compared to the original AES algorithm result, the suggested technique produces the expected results for several data types, including text, images, It is more important than ever to strengthen data protection procedures in an era of rising cyber dangers and growing reliance on digital data. A thorough framework for "Enhancing Data Protection through Advanced Encryption" (EDPAE) is introduced in this study. The project's goal is to protect sensitive data by utilizing state-of-the-art encryption techniques in response to the ever-changing cyber security scenario. In addition, the project places a strong emphasis on how to seamlessly incorporate advanced encryption into current data storage and communication systems in order to minimize interference with user operations and greatly improve overall security posture. In order to guarantee the secure creation, distribution, and storage of encryption keys and to reduce potential risks related to key compromise, key management features are addressed.

RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA

Finite field multiplication is a non-linear transformation operator that appears in the majority of symmetric cryptographic algorithms. Numerous specified finite field multiplication units have been proposed as a fundamental module in the coarse-grained reconfigurable cipher logic array to support more cryptographic algorithms; however, it will introduce low flexibility and high overhead, resulting in reduced performance of the coarse-grained reconfigurable cipher logic array. In this article, a high-flexibility and low-cost reconfigurable Galois field multiplication unit (RGMU) is proposed to balance the tradeoffs between the function, delay, and area. All the finite field multiplication operations, including maximum distance separable matrix multiplication, parallel update of Fibonacci linear feedback shift register, parallel update of Galois linear feedback shift register, and composite field multiplication, are analyzed and two basic operation components are abstracted. Further, a reconfigurable finite field multiplication computational model is established to demonstrate the efficacy of reconfigurable units and guide the design of RGMU with high performance. Finally, the overall architecture of RGMU and two multiplication circuits are introduced. Experimental results show that the RGMU can not only reduce the hardware overhead and power consumption but also has the unique advantage of satisfying all the finite field multiplication operations in symmetric cryptography algorithms.

Sequential logic circuit gold codes for electronics and communication technologies

The linear feedback shift register (LFSR) and Gold codes are used in telecommunications, Global Positioning System (GPS), satellite navigation, wireless systems, and code division multiple access (CDMA) dependent channel schemes for numerous radio communication technologies Gold codes are distinguished by their capacity to provide various orthogonal sequences.•The objective of the article is to focus on the design and simulation of the LFSR-based gold code generator chip in Xilinx ISE 14.7 software with the logic synthesis in Virtex-5 field programmable gate array (FPGA) and check the switching behavior with large frequency support applicable in fast-switching optical, and wireless electronics systems.•The methodology comprises design, functional simulation with different test inputs, and FPGA synthesis. The chip design is verified for the 10-bit seeding sequence of LFSRs to result in 1023-bit code with the frequency support of 310 MHz, and 9.285 ns delay.•The chip design is simulated based on seed data and different tap points of LFSR registers from which the bits are considered to generate the feedback. The design is scalable and has greater potential to extend to a larger extent. The behavior of the gold code depends on the maximum length sequence, absolute cross-correlation, and size of LFSR.

A color image encryption scheme based on cellular neural networks and linear feedback shift registers

In this paper, a cellular neural network (CNN) chaotic system is constructed and the multiple stability of the system and its rich chaotic properties are confirmed by studying the effect of parameters on the system, coexisting attractors, and offset boosting behavior. As linear feedback shift registers (LFSR) can be applied to cryptography, this paper applies LFSR to generate encrypted key matrices to enhance the randomness of encryption algorithms. Based on CNN and LFSR, a new color image encryption algorithm is designed by combining DNA coding and bit-plane decomposition with high bit-plane Zigzag dislocation changes. Experimental results and security tests show that the algorithm is highly secure and resistant to a variety of common attacks, such as differential attacks, cropping attacks, and noise attacks.

A search for short-period Tausworthe generators over F b with application to Markov chain quasi-Monte Carlo

ABSTRACT A one-dimensional sequence u 0 , u 1 , u 2 , … ∈ [ 0 , 1 ) is said to be completely uniformly distributed (CUD) if overlapping s-blocks ( u i , u i + 1 , … , u i + s − 1 ) , i = 0 , 1 , 2 , … , are uniformly distributed for every dimension s ≥ 1 . This concept naturally arises in Markov chain quasi-Monte Carlo (QMC). However, the definition of CUD sequences is not constructive, and thus there remains the problem of how to implement the Markov chain QMC algorithm in practice. Harase [A table of short-period Tausworthe generators for Markov chain quasi-Monte Carlo. J Comput Appl Math. 2021;384:Paper No. 113136, 12.] focussed on the t-value, which is a measure of uniformity widely used in the study of QMC, and implemented short-period Tausworthe generators (i.e. linear feedback shift register generators) over the two-element field F 2 that approximate CUD sequences by running for the entire period. In this paper, we generalize a search algorithm over F 2 to that over arbitrary finite fields F b with b elements and conduct a search for Tausworthe generators over F b with t-values zero (i.e. optimal) for dimension s = 3 and small for s ≥ 4 , especially in the case where b = 3, 4, and 5. We provide a parameter table of Tausworthe generators over F 4 , and report a comparison between our new generators over F 4 and existing generators over F 2 in numerical examples using Markov chain QMC.

Hybrid Efficient Stream Cipher KeyGenerator Based on LFSR's and Chaotic Map

Communication security that depends on chaos can be considered as a new approach which provides protection and security of communications and maintains confidentiality because Chaos theory can be implemented in cryptosystem successfully. A stream cipher, on the other hand, is a type of symmetric cryptosystem in which the plaintext is divided into small entities known as characters. The key in stream cipher is typically generated by a random bit generator. Many key stream generators employ linear feedback shift registers (LFSRs). LFSR systems are made up of a group of LFSR units and a combining function (CF) unit. The plaintext is encrypted one bit at a time. The key is fed into a random bit generator, which produces a long series of binary signals. This "key-stream" k is then combined with plaintext m, typically via a bit-wise XOR (Exclusive-OR modulo 2 addition), to produce the ciphertext stream, which employs the same random bit generator and seed. In this paper we will introduce a new stream cipher keygenerator which using a hybrid between chaotic and combination of Linear Feedback Shift Registers (LFSR's). The proposed generator can be used to protect different types of data files (text, image, audio and video). Many kinds of tests are applied to specifying the goodness of the proposed keygenerator. The results of testing prove the efficiency of the suggested system.

DISH: Digital image steganography using stochastic-computing with high-capacity

AbstractStochastic computing is a relatively new approach to computing that has gained interest in recent years due to its potential for low-power and high-noise environments. It is a method of computing that uses probability to represent and manipulate data, therefore it has applications in areas such as signal processing, machine learning, and cryptography. Stochastic steganography involves hiding a message within a cover image using a statistical model. Unlike traditional steganography techniques that use deterministic algorithms to embed the message, stochastic steganography uses a probabilistic approach to hide the message in a way that makes it difficult for an adversary to detect. Due to this error robustness and large bit streams stochastic computing, they are well suited for high capacity and secure image steganography. In this paper, as per the authors’ best knowledge, image steganography using stochastic computing based on linear feedback shift register (LFSR) is proposed for the first time. In the proposed technique, the cover image is converted to stochastic representation instead of the binary one, and then a secret image is embedded in it. The resulting stego image has a high PSNR value transmitted with no visual trace of the hidden image. The final results are stego image with PSNR starting from 30 dB and a maximum payload up to 40 bits per pixel (bpp) with an effective payload up to 28 bpp. The proposed method achieves high security and high capability of the number of stored bits in each pixel. Thus, the proposed method can prove a vital solution for high capacity and secure image steganography, which can then be extended to other types of steganography.

New Programmable LFSR Counters with Automatic Encoding and State Extension

An efficient method for detecting the end of a count of a linear feedback shift register (LFSR) is presented. We show how this detector can be used to extend a maximum-length LFSR sequence by a number of states up to one less than the degree of the polynomial. In addition, a new algorithm is proposed to encode binary sequence values into their corresponding LFSR sequence states. Based on this algorithm and an alternative second method, two novel programmable, full-range, high-speed LFSR counter designs are proposed. The time complexity of the conversion algorithms ranges from quadratic to exponential time in the degree of the underlying polynomial. The proposed counter solutions are fully synchronous and can be implemented with standard cells, enabling easy portability across technologies. As the levels of logic are independent of the counter size, high scalability is facilitated. For evaluation, all the designs, including the recreated state-of-the-art solution, have been implemented on an FPGA, and also simulated targeting TSMC’s N3 CMOS process node for a wide range of counter sizes. The results confirm the superiority of the proposed solutions over the state of the art in terms of frequency, area and power efficiency as the counter is scaled up.

Evaluation of Image Cryptography by Using Secret Session Key and SF Algorithm

In the unreliable domain of data communication, safeguarding information from unauthorized access is imperative. Given the widespread application of images across various fields, ensuring the confidentiality of image data holds paramount importance. This study centers on the session keys concept, addressing the challenge of key exchange between communicating parties through the development of a random-number generator based on the Linear Feedback Shift Register. Both encryption and decryption hinge on the Secure Force algorithm, supported by a generator. The proposed system outlined in this paper focuses on three key aspects. First, it addresses the generation of secure and randomly generated symmetric encryption keys. Second, it involves the ciphering of the secret image using the SF algorithm. Last, it deals with the extraction of the image by deciphering its encrypted version. The system’s performance is evaluated using image quality metrics, including histograms, peak signal-to-noise ratio, mean square error, normalized correlation, and normalized absolute error (NAE). These metrics provide insights into both encrypted and decrypted images, analyzing the extent to which the system preserves image quality. This assessment underscores the system’s capability to safeguard and maintain the confidentiality of images during data transmission.

A Response-Feedback-Based Strong PUF with Improved Strict Avalanche Criterion and Reliability.

Physical Unclonable Functions (PUFs) are significant in building lightweight Internet of Things (IoT) authentication protocols. However, PUFs are susceptible to attacks such as Machine-Learning(ML) modeling and statistical attacks. Researchers have conducted extensive research on the security of PUFs; however, existing PUFs do not always possess good statistical characteristics and few of them can achieve a balance between security and reliability. This article proposes a strong response-feedback PUF based on the Linear Feedback Shift Register (LFSR) and the Arbiter PUF (APUF). This structure not only resists existing ML modeling attacks but also exhibits good Strict Avalanche Criterion (SAC) and Generalized Strict Avalanche Criterion (GSAC). Additionally, we introduce a Two-Level Reliability Improvement (TLRI) method that achieves 95% reliability with less than 35% of the voting times and single-response generation cycles compared to the traditional pure majority voting method.

Designing New AES and Implementing it with LFSR Key to Improve Data Security

Data security is an essential aspect of data communication and data storage. The security and confidentiality of the information has become a significant factor in the communication field. To provide high-level security against all kinds of unauthorized accesses, cryptographic algorithms have been applied to various fields such as medical and military applications. Several techniques for encryption and decryption are proposed to promote the security of the communication systems. Most powerful and significant part of the encryption is a key generation. Presently, hackers are able to break the key with help of the modern high computing machines. Advanced Encryption Standard (AES), a symmetric cryptographic algorithm, is acknowledged as the most secure algorithm for the cryptographic process globally. In this work, Novel design and implementation of AES with LFSR (Linear Feedback Shift Register) key for improving data security is presented. The novelty of this work is using LFSR with AES. The Performance of presented approach is evaluated in terms of speed, area and security. The performance of presented technique will provide effective and efficient security to data.