Design Of Linear Feedback Shift Register Research Articles

A simultaneous area, delay and leakage current reduction method for Linear Feedback Shift Register (LFSR) using pulsed latches and DTMOS transistors

In digital circuits, the shift registers are the significant elements having the ability of storing and transmitting the data in sequential manner.The linear feedback shift register (LFSR) uses large number of flips-flops that consumes maximum amount of power. To overcome this issue, this research work concentrates on the design of LFSR for the area efficient, power reduction, minimization of delay and leakage current. By replacing the d-flip-flop with the bi-enabled pulsed latch to reduce the power consumption and delay of the proposed LFSR design. For the minimization of area, leakage current and delay, the hybrid body bias generator with dynamic threshold MOS (BBG-DTMOS) is used. Moreover, the pulsed clock signal is generated in the digital circuit with the aid of hybrid BBG-DTMOS technique. The proposed LFSR design is implemented in the tanner EDA tool with the available CMOS model libraries. Based on the implementation result, the proposed LFSR area is 1824 μm2and its power consumption is 172μW at a 100 MHz clock frequency withVDD=5V. Furthermore, having the better performance in different corners of the method, reduces the propagation delay and leakage current in the digital circuit. The proposed LFSR design is compared with some of the shift registers such as unidirectional and bidirectional shift registers. The existing clock pulse generator such as conventional, delayed clock pulse, TIMBER logic, PTL-AND logic and multiplexer based clock pulse generator (MCPG) are compared with the proposed BBG-DTMOS technique.

Design, Implementation and Performance Analysis of Test Pattern Generator for Built-In Self-Test using m-GDI Technology

Background: A Linear Feedback Shift Register (LFSR) is typically used for generating the test patterns in built-in self-test (BIST) as it produces pseudorandom patterns at every clock cycle. These pseudo-random patterns are used as test vectors for testing the VLSI circuits. Objective: The pseudorandom patterns generated by the LFSR exhibit low-correlation among the patterns, this increases the switching activity and power dissipation while testing the VLSI circuit. Thus, to reduce the testing power, modified gate diffusion input (m-GDI) logic based LFSR in 45nm technology is proposed in this paper. Methods: The circuits are developed on m-GDI technology using the Cadence virtuoso tool and a spectre simulator is used to carry out the simulation. Findings: Comparative analysis revealed that the delay and power are reduced significantly, for the proposed design when compared to the existing LFSRs in conventional CMOS, GDI and reversible logic. Novelty and applications: In conventional LFSR, an external source is necessary to load the seed value and it dissipates more power. But in the proposed design, the seed value is generated by the circuit itself. This reduces the power and critical path delay. Further a complete zero patterns is not possible in conventional LFSR design. But in proposed design, all zero pattern is plausible. The design obtained from this study can be applied in low-power, high-speed BIST circuits. Keywords: LFSR; Seed Value; Test Patterns; Built-In-Self-Test; m-GDI

VLSI Implementation of Linear Feedback Shift Register (LFSR) based Test Pattern Generator for Pseudo Exhaustive Testing

Advanced strides of improvement in programmable logic density, enhancements in speed and hardware description language (HDL) are empowering design engineers to implement highly performing and testable digital systems. Linear feedback shift registers (LFSR) are the critical elements in the testing and self testing of contemporary complex electronic systems like processors, Built-in-self-test (BIST) controllers and integrated circuits (ICs) etc. Fundamentally BIST is a Design-for-Testability (DFT) technique meant to configure testing functions physically with the circuit under test (CUT). To enhance the percentage of fault coverage as a part of BIST operations (testing the IC), LFSRs are deployed (as test pattern generator) to generate the test vectors inside logic BIST for testing digital systems. Proposed work is focused upon designing a fast adder based variable length pseudorandom binary sequence pattern generator (PRBSPG) and experimental validations. LFSR possess characteristics of high speed, better encoding efficiency, high fault coverage, low test volume data and low power consumption specially suitable in processing environment where uniform distribution random numbers are required. Verilog HDL is employed for structuring the modular design units while Xilinx ISE tool is deployed for validating the proposed LFSR design work and associated modular units.

Design of Pseudo Random Number Generator using Linear Feedback Shift Register

Nowadays security has become a great concern in the field of computer science and information technology. In order to protect data from unintended users and to achieve a desirable level of security, several cryptographic algorithms based on various technology have been proposed. Linear Feedback Shift Register (LFSR) may play an important role in the design of such cryptographic algorithms. LFSR based cryptographic algorithms are often lightweight in nature and are more suitable for resource constraining devices. In this paper we present a detailed analysis of LFSR and design of LFSR to implement cryptographic algorithms.

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

Low Power Implementation of Linear Feedback Shift Registers

This paper describes low power design and implementation of Linear Feedback Shift Register (LFSR). The easiness in implementation and simple operation of Linear Feedback Shift Register have made it fit into a wide range of digital systems design. Since random pattern generation, data encryption and decryption play a major role in communication systems, the LFSR comes into view for developing the patterns for these applications. As the need increases day after day, simple and high-performance design of LFSR is required. As power consumption of the device being an important factor in the VLSI circuits, it has to be reduced by including power optimization techniques in the designs. Pulsed Latch is a popular technique of reducing power consumption which uses Pulsed Latches instead of flip-flops. As latches have lesser number of circuit elements compared to flip-flops, the area is also minimized. By implementing this pulsed latch technique, the linear feedback shift register can be designed with low power and area. The design entry is done in VHDL code and implemented using Cadence tool. In Cadence, Nclaunch, RTL Complier and Encounter tools are used for simulation, synthesis and implementation. With this method, the power reduction is achieved up to 41.99%

Design of Feedback Shift Register of Against Power Analysis Attack

For simple hardware structure, high speed encryption and lower power consuming, stream ciphers well suited for constrained environments, such as satellite communications, RFID tag, sensor networks and IoT. Linear feedback shift register (LFSR) is widely used in the design of stream cipher to improve the periodic property of key stream. Since the switching of the status bits is regular, the power consumption of the LFSR is highly correlated in a linear way. The power consumption characteris-tics of stream cipher based on LFSR are vulnerable to leaking initialization vectors (IV) under the power attacks. Basing on the power model of LFSR, a new design of LFSR against power attacks is proposed in this paper. In this countermeasure, the power consumption characteristics of LFSR can be masked by using an additional LFSR and a new filter Boolean function. Compared with the others designs, this de-sign can confused the power consumption trace and can be more easily implemented by circuits.

Analysis, Design, and Test of CDMA LFSR with Offset Mask Using Standard ICs

Hardware implementation of Linear Feedback Shift Register (LFSR) plays a great and very important role in communication systems, and in many security devices. In this paper, a design of LFSR with offset mask has been presented, for Direct Sequence Code Division Multiple Access (DS-CDMA) applications. Integrated electronic components have been used. An accessible model facilitating the synthesis on Printed Circuit Boards (PCB) and implementation on Field Programmable Gate Array (FPGA) is offered. In addition, a temporal and spectral analysis of the circuit is performed in order to validate the design. This latter facilitates the generation of pseudo-random codes based on LFSR and their integration into electronic systems.

The $$k$$ -error linear complexity distribution for $$2^n$$ -periodic binary sequences

The linear complexity and the \(k\)-error linear complexity of a sequence have been used as important security measures for key stream sequence strength in linear feedback shift register design. By using the sieve method of combinatorics, we investigate the \(k\)-error linear complexity distribution of \(2^n\)-periodic binary sequences in this paper based on Games–Chan algorithm. First, for \(k=2,3\), the complete counting functions for the \(k\)-error linear complexity of \(2^n\)-periodic binary sequences (with linear complexity less than \(2^n\)) are characterized. Second, for \(k=3,4\), the complete counting functions for the \(k\)-error linear complexity of \(2^n\)-periodic binary sequences with linear complexity \(2^n\) are presented. Third, as a consequence of these results, the counting functions for the number of \(2^n\)-periodic binary sequences with the \(k\)-error linear complexity for \(k = 2\) and \(3\) are obtained.

A High- Speed LFSR Design by the Application of Sample Period Reduction Technique for BCH Encoder

Error correction is one of the important technique for detecting and correcting errors in communication channels, memories etc., BCH codes are widely been used for error detection and correction. The generated check bits of the BCH encoder along with the message bits called codeword is sent to the receiver to detect any error during the transmission. One of the main components of BCH encoder is LFSR (Linear Feedback Shift Register). LFSR find its wider application in Built-in-Self-Test, signature analyzer etc., whereas here it is used to form parity bits to concatenate with message bits for the formation of a codeword. The main advantage of LFSR is that it is simple to construct and it operates at very high clock speed, but its main drawback is that the inputs are given in bit serial. To overcome these drawbacks, DSP algorithms such as unfolding and parallel processing can be used by selecting the unfolding factor based on some design criteria. Selecting a better unfolding value reduces the sample period, decreases the clock cycle and increases the speed. .Keywords- Bose Chaudhuri-Hocquengham (BCH), Cyclic Redundancy Check (CRC), Computational Time (CT), Galois Field (GF), LFSR, unfolding, sample period reduction.

A built-in test pattern generator

Built-in testing is currently of more concern due to the difficulties in testing a VLSI by using an external tester. In addition, Built-In Testing is also necessary for on-line testing and a fault-tolerant computing system. Using a Linear Feedback Shift Register (LFSR) as a built-in test pattern generator (BITPG) is a realistic and simple approach. An LFSR with maximum length can generate pseudo-random test patterns or all non-null vectors for exhaustive testing. This paper presents an LFSR design with non-maximum length to serve as a BITPG to generate a given test setT, which efficiently saves testing time. A search-verification process for designing this kind of LFSR is employed and implemented by the program SVBITPG. This paper presents the diagram of the program and gives some examples to illustrate the design of the BITPG.