A High- Speed LFSR Design by the Application of Sample Period Reduction Technique for BCH Encoder

Abstract

Error correction is one of the important technique for detecting and correcting errors in communication channels, memories etc., BCH codes are widely been used for error detection and correction. The generated check bits of the BCH encoder along with the message bits called codeword is sent to the receiver to detect any error during the transmission. One of the main components of BCH encoder is LFSR (Linear Feedback Shift Register). LFSR find its wider application in Built-in-Self-Test, signature analyzer etc., whereas here it is used to form parity bits to concatenate with message bits for the formation of a codeword. The main advantage of LFSR is that it is simple to construct and it operates at very high clock speed, but its main drawback is that the inputs are given in bit serial. To overcome these drawbacks, DSP algorithms such as unfolding and parallel processing can be used by selecting the unfolding factor based on some design criteria. Selecting a better unfolding value reduces the sample period, decreases the clock cycle and increases the speed. .Keywords- Bose Chaudhuri-Hocquengham (BCH), Cyclic Redundancy Check (CRC), Computational Time (CT), Galois Field (GF), LFSR, unfolding, sample period reduction.