Linear Current Degradation Research Articles

Simulation study on radiation hardness for total ionizing dose effect of ultra-thin shielding layer 300 V SOI LDMOS

In this work, the linear current degradation mechanism of 300 V silicon-on-insulator laterally double-diffused metal-oxide-semiconductor field effect transistor under total ionizing effect is studied, and a method in radiation-hardness for linear current by introducing an ultra-thin shielding layer is proposed. This new structure is realized with P-type ultra-thin shielding layer implantation under field oxide, in order to prevent the P-type layer from complete surface inversion, thereby truncating the surface current route and mitigating the current degradation effectively. For a laterally double-diffused metal-oxide-semiconductor field effect transistor, linear current degradation can be attributed mainly to holes introduced in the field oxide. In this work, the influence of introduced holes on electrical properties in the transistor oxides under harsh environment is simulated based on device and process simulation software, with optimized layer length, implantation energy, lateral distance and dose window, and the goal of linear current hardness (linear current increment decreasing from 447% in conventional structure to less than 10% in proposed structure) is achieved while maintaining pre-rad and post-rad breakdown voltages above 300 V under total dose of 0–500 krad(Si).

Substrate current and degradation of trench LDD transistors

The substrate current and degradation behaviour of a novel trench LDD MOSFET, to be used as a high voltage device in the periphery of flash memories, is studied. At high drain voltage an unusual increase of the substrate current for high gate voltages is observed. Supported by device simulation this effect is attributed to the high series resistance of the device. The location of peak ionization rate is found to be shifted from the channel below the gate towards the trench LDD region. The degradation of linear current under several V GS stress conditions shows its maximum at gate voltages near the threshold voltage of the device.

Setting the trap for hot carriers [MOS VLSI

The device degradation under ac and dc stress have been discussed and a relationship between the two has been established,. We have shown that the commonly used lifetime criteria of 10% linear current degradation for 10 years for a transistor under dc stress is overly conservative for representing the circuit operating lifetime. Using experimental and simulated data for inverter chains, we proposed that a meaningful equivalent lifetime based on 10% I/sub dl/ degradation under dc stress is 1 year lifetime (for a 10 year circuit lifetime based on 54b degradation in ring oscillator frequency). We also compared this criteria to actual circuit degradation for microprocessors and a DRAM. For DSP microprocessors with 0.8 /spl mu/m LDD transistors, the projected lifetime was more than 200 years at 5.5 V, with a corresponding 10% I/sub dr/ lifetime of 20 years. For 1 Mb DRAMs with 1 pm LDD transistors, the 5% speed degradation lifetime at 5.5 V was more than 100 years, whereas the individual transistors had 10% I/sub dl/ lifetime of 4 years. These circuit results support the 10% I/sub dl/ transistor lifetime. We believe these criterion should be very safe and reasonable for digital IC chips currently in the field, as well as those in future design and development. >