Line Resistances Research Articles

A 3-D Circuit Model to evaluate CDM performance of ICs

This paper presents a physical description of the static charge flow through an IC during a CDM event. Based on this description, an equivalent 3-D circuit to model the complete IC under CDM stress is proposed. The model takes into account various factors like package parasitics, substrate resistance, parasitic contacts of the circuit elements with the substrate, bus line resistances, distribution of protection devices. It allows studying the influence of these factors on the voltage transients seen across the gate-oxides of MOS transistors. CDM measurements on an IC with rail based protection showed gate-oxide failure at the MOS transistors in the internal core circuitry. The proposed circuit model is applied to study the voltage transients between the internal MOS transistors gate and local substrate during CDM stress and thereby explain the reason for the observed gate-oxide failure. It is found that V SS line contact distribution with the substrate rail enhances CDM robustness, provided the power lines ( V SS and V DD line) are well clamped to each other.

A PVD based barrier technology for the 45 nm node

A new PVD source for barrier deposition has been developed which is extendible down to the 45 nm node. The source can conformally deposit barrier metal on the sidewalls of vias and trenches. The thickness of the barrier on the via bottom can be minimized for lowest via resistance. Electrical tests on typical back-end-of-line structures show line resistances consistent with measured trench sidewall coverage. Both stress migration and electro-migration performance are superior to previous generation PVD barrier sources.

Definitions of Apparent Power and Power Factor in a Power System Having Transmission Lines With Unequal Resistances

Recently, disputes in power theory seem to be settled and a new trial-use standard has been prepared as the IEEE Standard 1459-2000. However, since uniform line resistances are assumed, it is not enough not only for increasing transmission systems, such as parallel ac/dc systems, but for a three-phase four-wire system whose neutral line has a different thickness from the other lines. In this paper, a generalized power theory applicable to a system having transmission/distribution lines with unequal resistances is proposed, which is applicable to any kind of power system: from a single-phase system to a multiline system having transmission lines with equal or unequal resistances under asymmetric and/or nonsinusoidal conditions.

Impact of electroplated copper thickness on copper CMP and Cu/Coral™ BEOL integration

A study was carried out to establish the impact of electrochemical plated (ECP) Cu thickness on the effect of dishing during Cu chemical mechanical planarization and the electrical and reliability performance of 0.13 μm Cu/Coral devices. The roughness of Cu films at the wafer edge was found to increase with increasing film thickness while it remained constant at the wafer centre. This resulted in different Cu grain morphology across the wafers. The reduction in sheet resistance ( R s) for the Cu film after annealing, as well as the as-deposited and post annealed film stresses were also found to be dependent on the ECP Cu thickness. As the thickness increased, the R s reduction increased while the as-deposited and post annealed film stresses decreased. The different ECP Cu thickness did not show any significant difference in the amount of Cu dishing at the centre of the wafers. However, at the wafer edge, the Cu dishing amount was found to be significantly affected by the Cu thickness in which the amount of dishing increased as the thickness increased. The via chain, Kelvin via, M1 line and M2 line resistances also showed a strong dependence on the ECP Cu thickness. The thinnest Cu film of 0.7 μm gave the lowest results with the tightest spread for the four resistances tested. For the via chain and M1 line resistance, it was followed by the 1.0 μm Cu film and the 1.3 μm film yielded the worst data. In the case of Kelvin via and M2 line resistance, the thicker plated Cu films gave similar worse results. All the electrical results showed good coincidence with the Cu dishing data. The voltage ramp ( v-ramp) data showed no significant difference in the electrical field leading to dielectric breakdown at both M1 and M2 lines for all the three types of ECP Cu thickness split.

Maximising energy capture from distributed generators in weak networks

The paper discusses the implications of the increasing capacity of synchronous generators at the remote ends of rural distribution networks where the line resistances are high and the X/R ratios are low. Local voltage variation is specifically examined and two methods of compensation are proposed. The first of them is a deterministic system that uses a set of rules to switch intelligently between voltage and power factor control modes, while the second is based on a fuzzy inference system that adjusts the reference setting of the automatic power factor controller in response to the terminal voltage. Extensive simulations have verified that the proposed approaches may increase the export of real power while maintaining voltage within the statutory limits.

A direct Newton–Raphson economic emission dispatch

In this study, a direct Newton–Raphson method based on an alternative Jacobian matrix is proposed to solve the economic emission dispatch (EED) problem with line flow constraints. The alternative Jacobian matrix is formulated by the incremental transmission loss in terms of the sensitivity factors, line flows, and line resistances. The sensitivity factors are obtained from line flow solutions based on a DC load flow model. The proposed approach is tested on the Taiwan Power Company 288-bus system. Simulation results obtained from the proposed method confirm the advantage of computation rapidity and solution accuracy over that of the AC load flow method and the conventional B-coefficients method, respectively. The comparison confirms the capability of the proposed method in real-time implementation for the EED problem.

Multiobjective power dispatch with line flow constraints using the fast Newton-Raphson method

The fast Newton-Raphson approach based on an alternative Jacobian matrix is proposed to solve the power system multiobjective power dispatch (MPD) problem with line flow constraints. Two conflicting objectives including minimization of fuel cost and environmental impact of emission are considered in this study. The Jacobian matrix is formulated by the incremental transmission loss in terms of the sensitivity factors, line flows and line resistances. The sensitivity factors are obtained from line flow solutions based on a DC load flow model. Moreover, the B-coefficients matrix and the Lagrange function can be shown as convex functions. Therefore, the existence and uniqueness of the solution for the nonlinear equation of the MPD problem can be proven. The proposed approach is tested on the IEEE 14- and 30-bus systems. Simulation results obtained from the proposed method confirm the advantage of computation rapidity and solution accuracy over that of the AC load flow method and the conventional B-coefficients method, respectively. The comparison confirms the capability of the proposed method in real-time implementation for the MPD problem.

振動電圧法を用いたＡＭ‐ＬＣＤ用８ビットディジタルドライバの構成と動作原理

Devices and structures to resolve the issues of (1) die-size, (2) output deviations, and (3) power dissipation on an 8-bit digital data driver for AM-LCDs using an Alternating Voltage Drive (AVD) Method are reported. As voltage interpolation is performed by logical circuit in the AVD Method, device has been applied in the mechanism of determining the waveform in the voltage interpolative circuit and consequently the number of logical gates of an interpolative circuit has become less than that of a 6-bit driver. Concerning the output deviations, voltage deviations originated from line resistances are compensated by paired structures of voltage providing lines. This realized the output deviation characteristics that is less than half of the 6-bit driver. In order to suppress the increase of power dissipation, the frequency of the alternating voltage is increased gradually by 3 stages; thus, the 8-bit module has nearly same power dissipation as the 6-bit module.

振動電圧法による６ビットディジタルドライバの設計技術

An alternating voltage driving method (AVDM) for gray scale drive technology is proposed that utilizes the low-pass filter characteristics of the TFT-LCD to eliminate periodical components from alternating voltage and applies DC voltage which is represented as an average value to a pixel. This paper describes the structure of the AVDM six-bit driver and the logical design techniques used to create its output circuit, which is a voltage interpolating circuit. From evaluation of the low-pass filter effect, it is proved that most of the effect is produced by the time constant of the TFT and the pixel itself. It is confirmed that voltage deviations due to the line resistances in the driver die are a principal cause of the output deviations along with the low-pass filter effect. Design criteria for the voltage deviations are described. Last, the multiple AVDM is proposed for non-linear interpolation. A logical combinational method is described for applying it to a six-bit driver that needs 5 gray scale voltages.

General purpose fast decoupled power flow

A general purpose fast decoupled power flow model (GFDPF) is presented that exhibits more or less best convergence properties for both well-behaved and ill-conditioned systems. In the proposed model, all network shunts such as line charging, external shunts at buses, shunts formed due to π representation of off-nominal in-phase transformers etc. are treated as constant impedance loads. The effect of line resistances is considered while forming the [B′] matrix and are ignored in forming the [B″] matrix. This model is tested on several systems for both well-behaved and ill-conditioned situations. Simple, efficient compensation technique is proposed to deal with Q-limit enforcements associated with bus-type switchings at voltage-controlled buses. The results demonstrate that the proposed GFDPF model exhibits more or less stable convergence behaviour for both well-behaved and ill-conditioned situ ations.

Effects of neglecting resistances in XB and BX load-flow methods

Diakoptics, superposition, and the mismatch theorem are used to study theoretically the effect of neglecting line resistances when forming the various B matrices on the mismatches of the XB and the BX versions of the decoupled load-flow algorithms. The fixed Jacobian method (FJM) is used as a yardstick to compare the effectiveness of the XB and the BX versions. It is shown that the BX version is a better approximation to the FJM than the XB version for high r/x ratios. Results are reported using simulated networks.

A New Structure Preserving Energy Function Incorporating Transmission Line Resistances

A novel method to account for the transmission line resistances in structure preserving energy functions (SPEF) is presented in this paper. The method exploits the equivalence of a lossy network having the same conductance to susceptance ratio for all its elements to a lossless network with a new set of power injections. The system equations and the energy function are developed using centre of inertia (COI) variables and the loads are modelled as arbitrary functions of respective bus voltages. The application of SPEF to direct transient stability evaluation is presented considering a realistic power system example.

XXXVIII.Some experiments with carbon line resistances

XXXVIII.<i>Some experiments with carbon line resistances</i>