Line Driver Research Articles

An optical receiver for eight-level data communication over step index plastic optical fiber

An optical receiver with automatic-gain-control transimpedance amplifier, linear post amplifier and linear line driver suitable for multilevel signals is presented. A large-diameter photodiode (400 μm) with an antireflection coating optimized for red light was integrated. These features enable the presented optical receiver to be a promising plastic optical fiber receiver. An error free (<10 −8) 400 Mbit/s data rate over 50 m PMMA-step index plastic optical fiber (1 mm diameter) is achieved with eight-level pulse amplitude modulation (8-PAM).

High-/Mixed-Voltage RF and Analog CMOS Circuits Come of Age

Instead of blindly tracking the rapid downsizing of supply voltage (VDD) in technology scaling, high-/mixed-voltage radio-frequency (RF) and analog CMOS circuits have emerged as a prospective alternative comes of age. An elevated VDD, or a hybrid use of I/O and core VDD's, in conjunction with thinand thick-oxide MOS transistors open up many possibilities in defining circuit topologies, while maintaining the speed and area benefits of advanced processes. Circuit reliability can be guaranteed through advanced circuit techniques. This paper aims to provide a glimpse of the basic concept, system design considerations and circuit examples. A wide variety of RF and analog CMOS circuits designed based on such techniques are examined and new topologies are proposed. Those circuit topologies comprise the RF power amplifier, the low-noise amplifier, the mixer, operational-amplifier-based analog circuits, the sample-and-hold amplifier and, finally, the line driver. Reliability considerations such as oxide breakdown, hot carrier injection (HCI), time dependent dielectric breakdown (TDDB), and bias temperature instability (BTI) will be discussed, and their implications in different types of circuits will be justified. The outlined principles are extendable to other RF and analog circuits, motivating the adoption of new voltage-conscious topologies in ultrascaled CMOS processes.

Optical receiver for multicarrier modulation in short-reach communication

A high-linearity optical receiver with background-light-AGC for high PAPR signals is presented. The integrated BiCMOS optical receiver consists of a TIA with AGC, a linear amplifier and a line driver. The receiver THD is 1.7% and the third-order intermodulation is 50 dBc at 20 MHz and at an input optical power of −3.5 dBm. The third-order intermodulation decreases to 40 dBc at 100 MHz.

Full CMOS Single Supply PLC SoC ASIC with Integrated Analog Front-End

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ㎛ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 ㎃ at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 x 2.8 ㎟.

Fast and Offset-Leakage Insensitive Current-Mode Line Driver for Active Matrix Displays and Sensors

Current-programmed active matrix (AM) architectures that are independent of fabrication technology are attractive for display and sensor because of their ability to tolerate mismatches and nonuniformity caused by aging. However, the long settling time due to low current levels and large parasitic capacitance can be a significant limitation. In this paper, we present a fast current-mode line driver based on positive feedback which controls the effect of parasitic capacitance. The driver was fabricated in 0.8-mum 20-V CMOS technology. While the measured settling time of a conventional current source is around 2 ms for a 100-nA input current and 200-pF parasitic capacitance, it is less than 4 mus for the driver presented here. Moreover, an offset-leakage cancellation technique is implemented for the fabricated driver to reduce the effect of leakage and offset currents to few nA.

480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition

A resonant adiabatic mixed-signal VLSI array delivers 480 GMACS (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> multiply-and-accumulates per second) throughput for every mW of power, a 25-fold improvement over the energy efficiency obtained when resonant clock generator and line drivers are replaced with static CMOS drivers. Losses in resonant clock generation are minimized by activating switches between the LC tank and DC supply with a periodic pulse signal, and by minimizing the variability of the capacitive load to maintain resonance. We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load. The resonantly driven 256 times 512 array of 3-T charge-conserving multiply-accumulate cells is embedded in a template matching processor for image classification and validated in a face detection task.

Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects

PurposeThis paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects.Design/methodology/approachThe paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width.FindingsIt is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver.Originality/valueWhile designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

Impact of the variable output resistance on the transient response of LC transmission line CMOS buffers and its model

AbstractThe work focuses on the impact of the finite and variable MOSFET output resistance on the transient response LC transmission line drivers. Experimental results highlight the severe error occurring in conventional timing analysis when actual finite resistance of the device is neglected. A novel analytical model is presented to capture the variable resistance of the driver. The model allows closed‐form expressions for the output waveform to be carried out, and it agrees well with HSPICE simulations. The proposed model is suitable to figure fundamental timing parameters of CMOS gates driving lossless transmission lines, such as the propagation delay, transition time, as well as power estimation. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1504–1509, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22496

Experimental characterization of collapse-mode CMUT operation

This paper reports on the experimental characterization of collapse-mode operation of capacitive micromachined ultrasonic transducers (CMUTs). CMUTs are conventionally operated by applying a direct current (DC) bias voltage less than the collapse voltage of the membrane, so that the membrane is deflected toward the bottom electrode. In the conventional regime, there is no contact between the membrane and the substrate; the maximum alternating current (AC) displacement occurs at the center of the membrane. In collapse-mode operation, the DC bias voltage is first increased beyond the collapse voltage, then reduced without releasing the collapsed membrane. In collapse-mode operation, the center of the membrane is always in contact with the substrate. In the case of a circular membrane, the maximum AC displacement occurs along the ring formed between the center and the edge of the membrane. The experimental characterization presented in this paper includes impedance measurements in air, pulse-echo experiments in immersion, and one-way optical displacement measurements in immersion for both conventional and collapse-mode operations. A 205-microm x 205-microm 2-D CMUT array element composed of circular silicon nitride membranes is used in the experiments. In pulse-echo experiments, a custom integrated circuit (IC) comprising a pulse driver, a transmit/receive switch, a wideband low-noise preamplifier, and a line driver is used. By reducing the parasitic capacitance, the use of a custom IC enables pulse-echo measurements at high frequencies with a very small transducer. By comparing frequency response and efficiency of the transducer in conventional and collapse regimes, experimental results show that a collapsed membrane can be used to generate and detect ultrasound more efficiently than a membrane operated in the conventional mode. Furthermore, the center frequency of the collapsed membrane can be changed by varying the applied DC voltage. In this study, the center frequency of a collapsed transducer in immersion is shown to vary from 20 MHz to 28 MHz with applied DC bias; the same transducer operates at 10 MHz in the conventional mode. In conventional mode, the maximum peak-to-peak pressure is 370 kPa on the transducer surface for a 40-ns, 25-V unipolar pulse excitation. In collapse mode, a 25-ns, 25-V unipolar pulse generates 590 kPa pressure at the surface of the transducer.

과학기술위성 2호 Reaction Wheel Assembly Interface Unit Proto Flight Model 개발

과학기술위성 2호 사용되는 구동기인 반작용 휠(Reaction Wheel Assembly, RWA)과 위성 시스템을 연결해주는 인터페이스를 담당하는 Reaction Wheel Assembly Interface Unit(RIU)의 Proto Flight Model의 개발이 완료되고 동작시험을 마쳤다. RIU는 RWA에 공급되는 전원을 켜고 끄는 스위치와 명령을 주고 받는 위성탑재 컴퓨터(OBC)의 통신 회선을 선택하는 멀티플렉서, 그리고 RWA에 연결되는 물리적 통신라인으로 구성된다. Proto Flight Model of Reaction Wheel Assembly Interface Unit(RIU) for STSAT-2 was developed. The RIU of STSAT2 has three major functions for interface between satellite system and RWAs. It has switches for RWA main power, communication Mux. and communication line driver.

High-speed, address-encoding arbiter architecture

An address-encoding arbiter architecture is presented that is suitable for large asynchronous circuits requiring address event representation readout. It provides improvement in power and speed, while also reducing area. By encoding the address in each layer of the arbiter tree, the address line loads are distributed throughout the tree, thus reducing the maximum single load on a line driver.

Stress Mechanism about Field Lightning Surge of High Voltage BJT Based Line Driver for ADSL System

In this paper, we have verified stress root caused by lightning surge in High voltage BJT based line driver of ADSL telecommunication and created failure mechanism. To reproduce damages in Line driver, we have applied STD surge waveform in operating condition, which is specified in IEC-6000-4-5, to component and board level. Visual isolation for Damage root was conducted with Real-time Electrical Stress Analysis (RTESA) utilizing Photon Emission Microscopy (PEM). The surge made with input of Tx output created junction breakdown of amplifier, which is made of HVBJT cells, and also caused current crowding from Vcc (supply voltage). In case of Positive pulse, current crowding was observed from between Collector and Vcc (+)12V. For negative pulse, at between Emitter and Vee (−)12V, current crowding was found. For both cases, device damage level was the same. All of these could be considered as transient latchup phenomenon created in BJT cell. Applying temporary clamping diode to line driver Tx, we have conducted Board level surge injection test. As a result, with the correlation between surge level from component level reproduction test and the one from system level, we have decided field lightning surge damage level and set up line driver protection margin.

Behavioral analysis of self-oscillating class D line drivers

Self-oscillating power amplifiers (SOPAs) provide an elegant way to power signals which have high crest factors with a high efficiency. Recently, it has been shown that by pushing this concept to its limits, the stringent specifications of digital subscriber line (xDSL) could be met. For the design of these high bandwidth, low distortion amplifiers in a digital CMOS technology, a thorough analysis of the hard nonlinear system is mandatory. This paper describes behavioral models based on the describing function method and Bessel series expansion of nonlinear modulations. Models have been derived for the self-oscillation, the bandwidth, the dominant third-order distortion and all inter-modulation products of a SOPA line driver. All spectral peaks at the output of a single ended SOPA amplifier are qualitatively and quantitatively explained by these models with a very high accuracy. A calculation speed-up with three orders of magnitude could be obtained compared with a dedicated numerical simulator.

A Highly Linear and Large Bandwidth Fully Differential CMOS Line Driver Suitable for High-Speed Data Transmission Applications

This article describes a large bandwidth and low distortion line driver in a 0.35-μm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.

AC Measurement by Using an Optical Fiber Sensor

In this work the implementation of a sensor of optical fiber current is reported by means of a magnetic structure. The sensing element (magnetic structure) consists of a magnet placed in the center of a plastic membrane. The variation in the intensity of the light caused by a mirror adapted to the membrane allowed to detect the changes in the presence of a magnetic field produced by an alternating current. Its changes were detected optically. We design a circuit to convert the light to equivalent in data to be process by a PC. The data are read and by means of a program in software Labview®, is the equivalent of current according to the intensity of detected magnetic field. INTRODUCTION Accelerated changes in technology of systems of communications and arrival of systems optical that of way they replace to systems electronic that is used in this type of systems, have influenced to a great extent, so that we takes to the optic and in special case optical communications, like the door that opens new breaches and produces a great field of the investigation [2,3]. Many electronics devices like logic gates, elements of commutation and sensors, they have been replaced by optical fiber devices that have revolutionized of considerable way and which they surpass some restrictive of the electronic systems. The optical fibers are an average ideal to be used in atmospheres of high voltage of equal way, are ideal for the information transmission and taking advantage of this property also it is possible to be created devices that help us to take measurements. The conventional electrical systems are often inadequate in surroundings of high tensions and zones with interferents, local fields of industries with emanations, the optical fiber does not create east problem to us. The sensors of current based on optical fibers, are devices that are being studied and that have obtained good results [1]. ISSN 0040-2508 © 2005 Begell House, Inc. 691 J.M. ESTUDILLO-AYALA, R. ROJAS-LAGUNA,J.A. MARTIN-VELA E. ALVARADO-MENDEZ... The electronics devices to measure current discharges but unfortunately they are very expensive and that can well be alternative that they little by little allow to develop and to innovate sensors us of current done with optical fiber designed in schools of engineering for applications in electrical substations in the country, and measurements in the laboratory with greater exactitude. The sensors of current based on optical fiber have received a special attention in the recent years. This must to its immunity to the electromagnetic fields mainly; its hostile, low atmosphere robustness lost by the transmission of signals in long distances, possibility the multiplex of several signals, adjustable length of the sensible element, great bandwidth and dynamic range. They provide complete galvanic isolation when being an average dielectric; do not circulate around them electrical signals. DESIGN AND OPERATION Theory The sensor element consisted of a magnet placed in the center of a plastic membrane. The change in the intensity of the light caused by the mirror adapted to the membrane allowed to detect the changes in the presence of a magnetic field produced by an alternating current. If the implemented structure this located to a certain distance D of an electrical line driver, an electrical intensity Ielec, would be a force of Lorentz in the magnet. This force can be expressed like: m F MV H = ∇ . (1) With M and Vm being the magnetization and the volume of the magnet, respectively, and being the gradient of associated magnetic field to Ielec, the position of the magnet. If an ideal load line is considered, magnetic field H generated by Ielec to a distance D can be expressed in cylindrical coordinates like: ˆ 2 elec I B H u D θ μ π = = (2) from this expression, H ∇ it can be obtained like: 2 ˆ 2 elec r I H u D π ∇ = (3) In the equation 1 sample which the force that acts in the magnet indicates the direction of , that this throughout the radial axis. H ∇

15.3: Reliable Integrated a-Si Select Line Driver for 2.2-in. QVGA TFT-LCD

A 2.2″ QVGA a-Si TFT-LCD panel with reliable integrated a-Si select line driver (RASD) is demonstrated. The RASD makes it possible to perform an operation regardless the fluctuation in the threshold voltage of a-Si TFT-LCD after a long-term use. The RASD on glass substrate makes the dead space of TFT-LCD panel be further decreased.

Noise analysis of an Si-drift detector system with time-variant shaping

We report on the temperature and count-rate dependent noise behavior of an Si-drift detector system using an on-sensor integrated JFET in a source-follower configuration. The readout chain of a 0.8-/spl mu/m BiCMOS chip consists of a fully differential low-noise postamplifier, current-mode shaper with gated integrator, and analog storage cell. Six channels are processed in parallel using a 6 : 1 multiplexer buffered by a 100-/spl Omega/ line driver. The readout chain's power dissipation is /spl sim/15 mW/channel. The indexes for parallel, serial, and 1/f noise of the time-variant signal processor are calculated using weighting functions. For a detector capacitance of /spl sim/140 fF and low count rates, the chip's and total electronics' input-referred equivalent noise charge is about 20 and 23 rms electrons, respectively. Due to an almost quadratical increase of the noise indexes with increasing count rate, the signal current deteriorates so that the spectral resolution of a Cu-K/sub /spl alpha//-emission line at 20/spl deg/C decreases from /spl sim/300 eV (full-width at half-maximum) at low count rates to /spl sim/850 eV at 600 kilocounts per second. The investigation of the temperature-dependent leakage current for different detectors leads to current densities between 1.5 pA/mm/sup 2/ and 3 pA/mm/sup 2/ at 20/spl deg/C. The simulated and experimental data verify the theoretical results for a wide range of count rates and sensor temperatures.

A 0.13-/spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments

A 3.2-Gbit/s serializer prototype has been fabricated in a 0.13-/spl mu/m CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-/spl Omega/ line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B/10 B encoded for compatibility with commercial receivers. Radiation hardening layout techniques have been adopted, which guarantee radiation tolerant operation inside the innermost LHC detectors over more than 10 yr. This paper describes the circuit architecture and reports on the experimental results. Signal quality (jitter, noise floor, eye opening) and bit-error rate (BER) are measured at different transmission rates using laboratory instrumentation and dedicated test beds.

A CMOS line driver for ADSL central office applications

An ADSL central office (CO) line driver utilizing a single 6-V supply is described. The line driver output produces a 20-V/sub ppd/ signal to deliver a 40-V/sub ppd/ swing to a 100-/spl Omega/ line. The adoption of an active termination, a dynamic supply control circuit technique, and deep n-well devices at the output stage of the line driver is key in achieving such a large voltage swing in a 0.25-μm CMOS process. In order to ensure reliability of the output devices, the dynamic supply control algorithm is designed to activate only one lift amplifier at each signal path of the differential line driver at any given time. A transformer turns ratio of 1:2.4 ensures both reliability and optimal power dissipation in the presence of system losses. The total power dissipation of the line driver is 700 mW when discrete multitone signals with a crest factor of 15 dB were used to deliver 20.4 dBm to a 100-/spl Omega/ line.

A 610-mW zero-overhead class-G full-rate ADSL-CO line driver

With the drive to increase the number of ports that can be incorporated onto a single linecard in an ADSL Central Office (CO), and the consequent power consumption and thermal management issues that this increased density raises, power dissipation is a key parameter in the design of an ADSL modem. This paper presents a full-rate ADSL CO line driver, consuming 610 mW through active termination and a zero-overhead class-G technique. The supply switching scheme used features very low overhead voltage, logic control, and controlled supply rail ramp rate, and requires analog signal peak prediction be done on the digital data stream. The process used features dielectrically isolated silicon-on-insulator 0.7-μm complementary BiCMOS with thin-film resistors. The MOSFET class-G transistors operate in two modes for power efficiency and distortion control. The power consumption is 610 mW and the downstream missing tone power ratio is 69 dBC with 16-dB peak-to-average ratio support.