Line Cards Research Articles

Dynamic routing at different layers in IP-over-WDM networks — Maximizing energy savings

We estimate potential energy savings in IP-over-WDM networks achieved by switching off router line cards in low-demand hours. We compare three approaches to react on dynamics in the IP traffic over time, Fufl, Dufl and Dudl. They provide different levels of freedom in adjusting the routing of lightpaths in the WDM layer and the routing of demands in the IP layer. Using MILP models based on three realistic network topologies as well as realistic demands, power, and cost values, we show that already a simple monitoring of the lightpath utilization in order to deactivate empty line cards ( Fufl) may bring substantial benefits. The most significant savings, however, are achieved by rerouting traffic in the IP layer ( Dufl). A sophisticated reoptimization of the virtual topology and the routing in the optical and electrical domains for every demand scenario ( Dudl) yields nearly no additional profits in the considered networks. These results are independent of the ratio between the traffic demands and capacity granularity, the time scale, distribution of demands, and the network topology for Dufl and Dudl. The success of Fufl, however, depends on the spatial distribution of the traffic as well as on the ratio of traffic demands and lightpath capacity.

Energy optimization in IP-over-WDM networks

The energy crisis and environmental protection are gaining increasing concern in recent years. ICT (Information and Communication Technology) has a significant impact on the total electricity consumption all over the world. Telecom networks, being an important part of ICT, consume significant energy since more network equipment is deployed annually. Specifically, in IP-over-WDM networks, energy is consumed by network elements at both IP and WDM layers. Routers in the IP layer are the largest energy consumer in this architecture, and current network infrastructures have no energy-saving scheme, so a large amount of energy is wasted when traffic load is low. In this paper, we propose a novel approach to save energy in IP-over-WDM networks by shutting down idle line cards and chassis of routers based on time-of-the-day network traffic variation. A method based on Mixed Integer Linear Programming (MILP) is proposed to ensure that the energy cost incurred by the IP routers and optical cross-connects is minimized by our approach. We also propose some possible approaches to minimize potential traffic disruption when the network elements are shut down.

Integrated Restoration for Next-Generation IP-Over-Optical Networks

This paper describes work performed for the Defense Advanced Research Projects Agency CORONET-funded Protocols and Architectures for Resilient Agile Global Optical Networks project to build an integrated IP/optical layer (OL) restoration architecture that combines transponder-shared mesh restoration at the OL with innovative methods of using router line cards and OL reconfigurability to restore from a layer 3 outage. This is a significant advancement over current restoration strategies, which typically add significant additional layer 3 capacity (i.e., additional IP links) to allow all failures to be restored at layer 3 alone. The network and restoration architectures in the integrated restoration method are described, as are design methodologies for each layer. A realistic cost model is applied to demonstrate that the proposed integrated IP/OL restoration strategy may have significant cost advantages for a core IP network when compared to the commonly used restoration strategies today.

Can Simple Optical Switching Fabrics Scale to Terabit per Second Switch Capacities?

The design of fabrics for terabit packet switches and routers needs to consider the limitations imposed by electronic technologies. In particular, attention has to be paid to information density and to power consumption and dissipation, as well as to power supply and footprint requirements. Optical technologies can overcome some of these limitations. We analyze the use of optical fabrics to interconnect line cards in terabit packet switches and routers. For this purpose, single-plane and multiplane optical interconnection architectures are proposed that exploit wavelength agility at line cards to implement the required switching functionality. The physical-layer scalability and feasibility of these architectures are studied by using realistic models, mostly based on the characteristics of commercially available optoelectronic devices. As a result, the considered architectures can be characterized in terms of power budget and signal-to-noise ratio, enabling the computation of the maximum achievable port count and aggregate switching capacity. Our results show that aggregate capacities of the order of a few terabits per second are possible in very simple optical switching fabrics and that the multiplane architectures permit a complexity trade-off between the wavelength and space domains, making the overall design more feasible.

Off-chip communication architectures for high throughput network processors

In this paper, we propose a new interconnection mechanism for network line cards. We project that the packet storage needs for the next-generation networks will be much higher. Such that the number of memory modules required to store the packets will be more than that can be directly connected to the network processor (NPU). In other words, the NPU I/O pins are limited and they do not scale well with the growing number of memory modules and processing elements employed on the network line cards. As a result, we propose to explore more suitable off-chip interconnect and communication mechanisms that will replace the existing systems and that will provide extraordinary high throughput. In particular, we investigate if the packet-switched k-ary n-cube networks can be a solution. To the best of our knowledge, this is the first time, the k-ary n-cube networks are used on a board. We investigate multiple k-ary n-cube based interconnects and include a variation of 2-ary 3-cube interconnect called the 3D-mesh. All of the k-ary n-cube interconnects include multiple, highly efficient techniques to route, switch, and control packet flows in order to minimize congestion spots and packet loss within the interconnects. We explore the tradeoffs between implementation constraints and performance. Performance results show that k-ary n-cube topologies significantly outperform the existing line card interconnects and they are able to sustain higher traffic loads. Furthermore, the 3D-mesh reaches the highest performance results of all interconnects and allows future scalability to adopt more memories and/or processors to increase the line card’s processing power.

Trends in highly scalable crossbar-based packet switch architecture

A combined input and crosspoint queued (CICQ) switch is receiving significant attention to be the next generation high speed packet switch for its scalability; however, a multi-cabinet implementation of a combined input and crosspoint queued (CICQ) switch unavoidably introduces a large round-trip time (RTT) latency between the line cards and switch fabric, resulting a large crosspoint (CP) buffer requirement. In this paper, virtual crosspoint queues (VCQs) that significantly reduces the CP buffer requirement of the CICQ switch is investigated. The VCQs unit resides inside the switch fabric, is dynamically shared among virtual output queues (VOQ) from the same source port, and is operated at the line rate, making the implementation practical. A threshold-based exhaustive round-robin (T-ERR) arbitration is employed to reduce buffer hogging at VCQ. The T-ERR at VCQ and CP arbiters serves packets residing in a longer queue more frequently than packet residing in a shorter queue. Consequently, the T-ERR, drastically increases the throughput of the CICQ switch with small CP buffers. A multi-cabinet implementation of CICQ switch do not support multicasting traffic well since a combination of small CP buffer in the switch fabric and a large RTT latency between the line cards and switch fabric results in non-work conservation of the intra-switch link. Deployment of multicast FIFO buffer between the input buffer and CP buffer shows a promise. With its ability to achieve high throughput independent of RTT and switch port size, the integration of the VCQ architecture and T-ERR scheduler to the CICQ switch is ideal for supporting ever-increasing Internet traffic that requires higher data rate, larger switch size, and efficient multicasting.

A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents the architecture and circuit design of a single chip 32 mm<formula formulatype="inline"><tex Notation="TeX">$^2$</tex></formula> 90 nm CMOS DSP transceiver for electronic dispersion compensation (EDC) of multimode fibers at 10 Gb/s, based on maximum likelihood sequence detection (MLSD). This is the first MLSD-based transceiver for multimode fibers and the first fully integrated DSP based transceiver for optical channels reported in the technical literature. The digital receiver incorporates equalization, Viterbi detection, channel estimation, timing recovery, and gain control functions. The analog front-end incorporates an 8-way interleaved ADC with self-calibration, a programmable gain amplifier, a phase interpolator, and the transmitter. Also integrated are a XAUI interface, the physical coding sublayer (PCS), and miscellaneous test and control functions. Experimental results using the stressors specified by the IEEE 10 GBASE-LRM standard <citerefgrp><citeref refid="ref1"/></citerefgrp>, as well as industry-defined worst-case fibers are reported. A sensitivity of <formula formulatype="inline"><tex Notation="TeX">${-}$</tex> </formula>13.68 dBm is demonstrated for the symmetric stressor of <citerefgrp> <citeref refid="ref1"/></citerefgrp> in a line card application with a 6 inch FR4 interconnect. </para>

Specification and Verification of Soft Error Performance in Reliable Internet Core Routers

This paper presents a methodology for developing a specification for soft error performance of an integrated hardware/software system that must achieve highly reliable operation. The methodology enables tradeoffs between reliability and cost to be made during the early silicon design and SW architecture phase. An accelerated measurement technique using neutron beam irradiation is also described that ties the final system performance to the reliability model and specification. The methodology is illustrated for the design of a line card for an internet core router.

Research on Next-Generation Scalable Routers Implemented with H-Torus Topology

The exponential growth of user traffic has been driving routers to run at higher capacity. In a traditional router, the centralized switching fabric is becoming the bottleneck for its limited number of ports and complicated scheduling algorithms. Direct networks, such as 3-D Torus topology, have been successfully applied to the design of scalable routers. They show good scalability and fault tolerance. Unfortunately, its scalability is limited in practice. In this paper, we introduce another type of direct network, called H-Torus. This network shows excellent topological properties. On its basis, the designs of line card and routing algorithms are introduced. Extensive simulations show that the routing algorithm is very important in such a system and results in low latency with high throughput.

On Guaranteed Smooth Switching for Buffered Crossbar Switches

Scalability considerations drive the evolution of switch design from output queueing to input queueing and further to combined input and crosspoint queueing (CICQ). However, CICQ switches with credit-based flow control face new challenges of scalability and predictability. In this paper, we propose a novel approach of rate-based smoothed switching, and design a CICQ switch called the smoothed buffered crossbar or sBUX. First, the concept of smoothness is developed from two complementary perspectives of covering and spacing, which, commonly known as fairness and jitter, are unified in the same model. Second, a smoothed multiplexer sMUX is designed that allocates bandwidth among competing flows sharing a link and guarantees almost ideal smoothness for each flow. Third, the buffered crossbar sBUX is designed that uses the scheduler sMUX at each input and output, and a two-cell buffer at each crosspoint. It is proved that sBUX guarantees 100% throughput for real-time services and almost ideal smoothness for each flow. Fourth, an on-line bandwidth regulator is designed that periodically estimates bandwidth demand and generates admissible allocations, which enables sBUX to support best-effort services. Simulation shows almost 100% throughput and multi-microsecond average delay. In particular, neither credit-based flow control nor speedup is used, and arbitrary fabric-internal latency is allowed between line cards and the switch core, simplifying the switch implementation.

A distributed and scalable routing table manager for the next generation of IP routers

In recent years, the exponential growth of Internet users with increased bandwidth requirements has led to the emergence of the next generation of IP routers. Distributed architecture is one of the promising trends providing petabit routers with a large switching capacity and high-speed interfaces. Distributed routers are designed with an optical switch fabric interconnecting line and control cards. Computing and memory resources are available on both control and line cards to perform routing and forwarding tasks. This new hardware architecture is not efficiently utilized by the traditional software models where a single control card is responsible for all routing and management operations. The routing table manager plays an extremely critical role by managing routing information and in particular, a forwarding information table. This article presents a distributed architecture set up around a distributed and scalable routing table manager. This architecture also comes provides improvements in robustness and resiliency. The proposed architecture is based on a sharing mechanism between control and line cards and is able to meet the scalability requirements for route computations, notifications, and advertisements. A comparative scalability evaluation is made between distributed and centralized architectures in terms of required memory and computing resources.

CR: Scalable Routers Based on a New Architecture

The switching fabric in the Avici TSR uses a 3-D torus topology with each line card carrying one node of the torus. It requires no centralized switching fabric, whereas its scalability is limited by the bisection bandwidth. This paper proposes a novel architecture called Cellular Router (CR). There exist some problems with the basic CR architecture. They are solved by introducing Mirror Points (MPs). This paper also gives the design of line cards in this architecture. In the end, the design of routing algorithms is introduced on this architecture. The CR architecture shows excellent scalability and fault tolerance. It is a promising choice for the design of scalable routers.

Integration technologies for pluggable backplane optical interconnect systems

Integration technologies for board-to-board optical interconnect systems are presented. In the module architecture, optical transmitters and receivers are placed on the line cards and the signals are routed to the optically passive backplane through optical jumpers. The backplane contains a light guiding layer with embedded polymer waveguides (WGs) and 45-deg reflector micromirrors. The WGs are fabricated by direct lithographic patterning and have propagation losses as low as 0.05 dB/cm. The wedge dicing technology is developed for fabrication of the 45-deg micromirrors with 0.5-dB excess losses. The pluggable optical connectors with microlens adaptors couple the light from the optical jumpers into the backplane WGs. Evaluation of the connector alignment tolerances demonstrates a very weak dependence of the coupling efficiency on the axial displacement and a more significant effect of the radial shifts. The presented results show that the displacement tolerances can be substantially improved with auxiliary lenses formed on the substrate. Prototype optical interconnect modules with integrated channel WGs, mirrors, and assembled connectors are fabricated with insertion losses of 5 to 6 dB. The modules successfully pass the high-speed transmission tests at data rates up to 11 Gbits/s.

Implementation of Scalable Routers with Direct Networks

In the Internet,the exponential growth of user traffic has been driving routers to run at higher capacity. Traditional routers consist of line cards and centralized switching fabrics. The centralized switching fabric in such a router,however,is becoming the bottleneck for its limited port numbers and complicated scheduling algorithms. In addition,the fabric is the single point of failure (SPF) in the router. Direct networks,such as 3-D Torus topology,have been successfully applied to the design of scalable routers. They show good scalability and fault tolerance. Unfortunately,its scalability is limited in practice. This paper introduces another type of direct network,called cellular router (CR). With a little modification,this network shows excellent topological properties. Based on this network,two classes of minimal routing algorithms are introduced. The load-balanced minimal routing (LBMR) algorithm makes use of path diversity and shows low latency and high throughput on both uniform random (UR) and Tornado traffic. This paper also discusses some other aspects of the routing algorithms,such as effects of queue length and scheduling algorithms. The CR architecture is a promising choice for the design of scalable routers.

Fast comms clocks get the digital treatment

The various 10Gb/s communications protocols look very similar until you get to the clocking systems they need. A digital approach to dock generation can make those differences much easier to deal with and let you produce more flexible line cards. As both business and residential customers demand greater access to high-speed network services, equipment suppliers are searching ways to provide low cost, multi-protocol interfaces that can quickly be provisioned for use. A prime example of this trend is the convergence of various data rates in the vicinity of 10Gb/s that can all share much of the same hardware and optics, even though each is generated by different protocols.

Gaussian tandem queues with an application to dimensioning of switch fabric interfaces

Tandem systems are seen in many places and at various hierarchical levels in high-speed communication networks, from router architectures to protocol stacks. If the traffic fed into the system is generated by independent or weakly dependent sources and the smallest relevant time scale is not too fine, the central limit theorem suggests that the input traffic is (close to) Gaussian. This paper considers tandem queues fed by Gaussian processes with stationary increments. Relying on the generalized version of Schilder's sample-path large-deviations theorem, we derive the many-sources asymptotics of the overflow probabilities in the second queue; 'Schilder' reduces this problem to finding the most probable path along which the second queue reaches overflow. The general form of these paths is described by recently obtained results on infinite-intersections of events in Gaussian processes; for the special cases of fractional Brownian motion and integrated Ornstein-Uhlenbeck input, the most probable path can be explicitly determined, as well as the corresponding exponential decay rate. As the computation of the decay rate is numerically involved, we introduce an explicit approximation ('rough full-link approximation'). Based on this approximation, we propose performance formulae for network provisioning purposes. Simulation is used to assess the accuracy of the formulae. As an example, we show how the methods can be applied to dimensioning the interface between a line card and a switch fabric.

Experimental use of code delta, code churn, and rate of change to understand software product line evolution

This research is a longitudinal study of change processes. It links changes in the product line architecture of a large telecommunications equipment supplier with the company’s customers, inner context, and eight line card products over six-year period. There are three important time related constructs in this study: the time it takes to develop a new product line release; the frequency in which a metric is collected; and the frequency at which financial results and metrics related to the customer layer are collected and made available. Data collection has been organized by product release. The original goal of this research is to study the economic impact of market reposition on the product line and identify metrics that can be used to records changes in product line. We later look at the product line evolution vis-à-vis the changes in the products that form the product line. Our results show that there is no relationship between the size of the code added to the product line and the number of designers required to develop and test it; and there is a positive relationship between designer turnover and impact of change.

Modelling and simulation of off-chip communication architectures for high-speed packet processors

In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications architectures for line cards. The simulator uses the state-of-the-art software design techniques to provide the user with a flexible, robust and comprehensive tool that can evaluate k-ary n-cube based network topologies under non-uniform traffic patterns. The simulator provides full control over essential network parameters and flow control mechanisms such as virtual channels and sub-channeling. We compare three low-dimensional k-ary n-cube based interconnects that can fit into the physical limitations on line cards, where each one of these interconnects has multiple processor-memory configurations. Performance results show that k-ary n-cube architectures perform better than existing interconnects, and they can sustain current line rates and higher. In addition, we provide performance tradeoffs between multiple flow control mechanisms and performance metrics such as throughput, routing accuracy, failure rate and interconnect utilization.

Routing table partitioning for speedy packet lookups in scalable routers

Most of the high-performance routers available commercially these days equip each of their line cards (LCs) with a forwarding engine (FE) to perform table lookups locally. This work introduces and evaluates a technique for speedy packet lookups, called SPAL, in such routers. The BGP routing table under SPAL is fragmented into subsets which constitute forwarding tables for different FEs so that the number of table entries in each FE drops as the router grows. This reduction in the forwarding table size drastically lowers the amount of SRAM (e.g., L3 data cache) required in each LC to hold the trie constructed according to the prefix matching algorithm. SPAL calls for caching the lookup result of a given IP address at its home LC (denoted by LC/sub ho/, using the LR-cache), such that the result can satisfy the lookup requests for the same address from not only LC/sub ho/, but also other LCs quickly. Our trace-driven simulation reveals that SPAL leads to improved mean lookup performance by a factor of at least 2.5 (or 4.3) for a router with three (or 16) LCs, if the LR-cache contains 4K blocks. SPAL achieves this significant improvement, while greatly lowering the SRAM (i.e., the L3 data cache plus the LR-cache combined) requirement in each LC and possibly shortening the worst-case lookup time (thanks to fewer memory accesses during longest-prefix matching search) when compared with a current router without partitioning the routing table. It promises good scalability (with respect to routing table growth) and exhibits a small mean lookup time per packet. With its ability to speed up packet lookup performance while lowering overall SRAM substantially, SPAL is ideally applicable to the new generation of scalable high-performance routers.

Dynamically reconfigurable optical packet switch (DROPS)

A novel Dynamically Reconfigurable Optical Packet Switch (DROPS) that combines both spectral and spatial switching capabilities is proposed and experimentally demonstrated for the first time. Compared with an Arrayed Waveguide Grating Router (AWGR), the added spatial switching capability provided by the microelectromechanical systems (MEMS) enables dynamically reconfigurable routing that is not possible with an AWGR alone. This methodology has several advantages over an AWGR including scalability, additional degrees of freedom in routing a packet from an ingress port to an egress port and more flexibility in path or line card recovery. The experimental demonstration implemented with 10-Gb/s packets shows that the added spatial switching does not degrade the bit-error-rate performance, indicating the promising potential of DROPS as a versatile and ultra-high capacity switch for optical packet-switched networks.