Fault Current Limiter Research Articles

A Comparative Study on Applicability of Parallel Resonance Type Fault Current Limiters in Power Systems

A Comparative Study on Applicability of Parallel Resonance Type Fault Current Limiters in Power Systems

A nonlinear model predictive controller design for residual current compensation inverters in rapid earth fault current limiters to mitigate powerline bushfires

This paper presents a nonlinear model predictive control scheme for residual current compensation inverters in rapid earth fault current limiters to inject appropriate current to the neutral so that the fault current is compensated in distribution networks. The proposed nonlinear model predictive controller is designed to limit the fault current within a level that powerline bushfires do not ignite due to single line-to-ground faults on power distribution systems in bushfire prone areas. The nonlinear model predictive controller is designed for a T-type residual current compensation inverter in rapid earth fault current limiters based on its dynamical model where the control objective is to inject current for compensating the fault current. The control law for the residual current compensation inverter is obtained by solving an optimal control problem while using the concept of the receding horizon control scheme. The performance of the controller is evaluated through standard software-based computer and processor-in-loop simulations where results are benchmarked against backstepping and sliding mode controllers in terms of compensating both faulty phase voltage and fault current.

Improving the Performance of PMSG Wind Turbines During Grid Fault Considering Different Strategies of Fault Current Limiters

The wind energy conversion technology of a Permanent Magnet Synchronous Generator (PMSG) is very promising in renewable power generation. However, the performance of the grid-connected PMSGs is greatly affected by grid disturbances because their stator windings are interfaced with the grid directly. There are different Fault Current Limiter (FCL) topologies that are capable of improving the Fault Ride Through (FRT) capability of PMSG wind turbines during short circuit faults. This study investigates three types of FCLs connected to the grid side of the PMSG wind turbine: Series Dynamic Braking Resistor (SDBR), traditional Bridge Fault Current Limiter (BFCL), and Capacitive Bridge Fault Current Limiter (CBFCL). Complete modeling of FCLs was derived in order to understand their behaviors accurately during normal conditions and fault periods. The performance of the three FCLs in the PMSG wind turbine was analyzed and compared using a severe three-phase to ground fault at the terminal of the PMSG wind turbine in Power System Computer Design and Electromagnetic Transient Including DC (PSCAD/EMTDC) platform. The same conditions of operation were used in investigating the various FCL strategies in the PMSG wind turbine considered in this study during grid fault for effective comparison.

Flexible Fault Current Adaptation Features of a Novel DC Circuit Breaker Assisted by Superconducting Fault Current Limiters

The high d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> before zero-crossings easily leads to delayed or failed operations for the active current injection mechanical DC circuit breaker, especially for small direct current interruptions. The pre-charging process also makes this type of circuit breaker hard to realize repeat operations economically in the high voltage DC system. This paper proposes a novel DC circuit breaker and its design method that deeply coordinating a superconducting fault current limiter with the active current injection DC circuit breaker. This method significantly reduces d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> before current zero-crossings and enables repeat operations economically. Besides limiting fault currents, the superconducting fault current limiter also charges the resonance capacitor flexibly in the circuit breaker, realizing the injected reverse current keep a constant proportion to the arbitrary fault current. Validations of the flexible capacitor charge and repeat operations are made by simulation and low voltage experiments. The charging times are within 2.5 ms and the reverse current keeps 1.2 to 1.7 times over the fault current under arbitrary conditions. D <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> at current zero is reduced by 80% under 30% of rated interruption capacity. Flexible capacitor charge experiments are consistent with the simulation design. The superconducting tapes can recover within 300 ms to support repeat operations.

Numerical Study on the On-Grid Performance of Superconducting Cable Cooperated With R-SFCL

The high temperature superconducting (HTS) cable has shown promising prospects in megacities for the advantages of high transmission power density and low loss. However, when HTS cable is working on grid, various kinds of faults may cause irreversible damage, resulting in the failure of reclosing. In this paper, the resistive superconducting fault current limiter (R-SFCL) is introduced into the power system to cooperate with the HTS cable, so as to reduce the potential damage caused by fault current. Firstly, the equivalent circuit models are established, and then transient response of HTS cables under fault condition is analyzed, the recovery time of HTS tapes are used to define the design of R-SFCL. Finally, the operating reliability of HTS cable has been evaluated and measures about adaptive reclosing times were proposed under different fault currents.

Formation of Hot Spots in Coated Conductors During Static and Dynamic DC Loading

High voltage DC transport at long distances represents an opportunity for wider use of superconductors. In particular, the second generation of high temperature superconductor tapes produced in form of coated conductors (CC) offers a unique solution for protecting a high-capacity connection against fault currents. In the resistive superconducting fault current limiter (R-SFCL), the CC tape would emerge as a substantial resistance in case of overcoming its critical current, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_c</i> . Non-uniformity of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_c</i> along the CC length is a common issue requiring attention. Because of highly nonlinear current/voltage dependence, the spot with critical current <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_cmin</i> < <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_c</i> could transform into the hot spot with rapid rise of local temperature. Due to its small dimension, it would not create an observable voltage at the device terminals, thus may escape attention of a quench detection system. We have investigated the mechanism of hot spot creation at the DC currents between <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_cmin</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_c</i> , and the analytical formulas have been derived predicting the limits of stable operation. Now we extend the analysis to the case of the limitation event, when for a fraction of second the current exceeds also the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_c</i> . It is desirable that the temperature rise happens along all the conductor length, leading to a quick reduction of transported DC. Numerical modelling has been utilized to analyze such an event, and a simplified analytical model has been developed to predict the range of currents causing the formation of hot spots.

Study of Resistive Superconducting Fault Current Limiters for Stability Improvement of VSG-Controlled Multiple Microgrid Clusters

Multiple microgrid (multi-MG) clusters based on virtual synchronous generator (VSG) control can preferably incorporate renewable energies. Nevertheless, the power angle stability (PAS) of VSG–controlled multi-MG clusters is easy to be influenced by grid faults. In this paper, resistive superconducting fault current limiters (R–SFCLs) are introduced to deal with this PAS problem. It is designed to install the R-SFCLs at the point of common coupling (PCC) of each MG in the clusters. The transient stability mechanism based on power balance and swing equation is analyzed to clarify the impacts of the R-SFCLs. Through MATLAB, a simulation model of three VSG-controlled MGs with R-SFCLs is built, and different fault scenarios are imitated for checking the performance behaviors of the R-SFCLs. From the simulation results, the R-SFCLs can visibly suppress the overcurrent inrush and assist the MGs in the clusters to fulfill the fault-ride through (FRT). Moreover, the energy dissipation of the R–SFCLs is calculated, and an improved power balance property is obtained in the multi-MG clusters to alleviate the power-angle fluctuations. Consequently, the effectiveness of the R–SFCLs on reducing the relative power angle variation is demonstrated, and the transient stability of the multi-MG clusters withstanding the three-phase faults is favorably enhanced.

Some Results of the EU Project FASTGRID

The EU FASTGRID project aimed at improving the REBCO conductor in order to enhance its economical attractiveness for the Superconducting Fault Current Limiter (SFCL). Two approaches were simultaneously investigated: i) the reduction of the tape length through the increase of the electric field during limitation, ii) the reduction of the tape cost through improved yield and higher critical current, including the lowering of the liquid nitrogen bath temperature to 65 K. We carried out a base line using an upgraded THEVA tape. Different approaches have been tried to improve the shunt layer, both with metallic and non-conductive materials. As a first solution, we developed and successfully tested a conductor with a Hastelloy shunt able to withstand 130 Vrms/m during 50 ms at 65 K and low prospective current faults. This conductor was used in two pancake coils. These have been successfully tested at IPH in Berlin. The second shunt solution developed consisted of a ceramic in epoxy matrix coating. Another significant improvement of the tape is the successful implementation of the Current Flow Diverter (CFD) concept with a simple sulfidation process or a deposition of an insulating yttria nanolayer by Inkjet Printing. An increase by one order of magnitude of the Normal Zone Propagation Velocity with respect to tapes without CFD has been measured. A low cost and fast hot spot detection system has also been developed. To reach much higher electric fields under limitation, the FASTGRID team also developed advanced tapes based on a sapphire substrate, which can tolerate ultra-high electric fields up to about 1 kV/m. Validated at laboratory scale, this game-changing technology needs to be implemented in long lengths with an industrial process. One pancake was integrated and tested with a low-cost optical fiber and fast hot spot detection system, developed and patented within the FASTGRID project. This manuscript will showcase most of these FASTGRID results.

Numerical Simulation of Thermal Stabilization Used in HTS Tapes for SCFCL Application

Resistive superconducting fault current limiters (R-SCFCL) are novel devices which implement high-temperature superconducting (HTS) tapes. Unfortunately, the tapes in as-delivery state cannot withstand higher electric fields and thus high temperatures during a quench event, so they must be modified by a thermal stabilization layer. Detailed thermal finite-element (FE) analysis was carried out using the finite element modeling software (FEM SW) ANSYS, to investigate the heat transfer in ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</b> ) high-heat capacity materials applied on the HTS tapes, as well as in (2) the HTS tapes themselves. The individual models differ in materials of thermal stabilization, thicknesses and geometry configuration. Their thermal behavior was investigated under different quenching temperatures. Numerical simulations proved that epoxy composite filled with 20 vol.% of SiC particles as a filler in form of 100 μm thick overlayer coating is a promising high-heat capacity material, suitable for the thermal stabilization of HTS tapes in R-SCFCL application.

An Improved Submodule Topology of MMC With Fault Blocking Capability Based On Reverse-Blocking Insulated Gate Bipolar Transistor

The missing capability of DC fault current limitation is an inherent disadvantage in the typical half-bridge modular multilevel converter (MMC), which restricts its application in long-distance high voltage direct current (HVDC) systems. The full-bridge submodule (FBSM) and clamped double submodule (CDSM) topologies allow for fault current self-clearing, but also suffer from additional hardware cost and power losses. In this paper, an improved submodule topology utilizing the new reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed to improve system economy without compromising its performance. The operating principles and DC fault characteristics of the proposed topology are analyzed in details, including comparison with various topologies in terms of cost, losses, fault current clearing speed and thermal. Compared with the traditional CDSM topology, the proposed RBSM can clear DC faults faster with reduced cost of switching devices. A DC fault protection strategy for MMC-HVDC system is also presented. Simulation results under normal operating, permanent and transient fault conditions are carried out to verify the effectiveness of the proposed topology.

Impact of Current Transfer to Porous Stabilizer on Recovery Performance of Resistive-Type Superconducting Fault Current Limiters Using REBCO Tapes

Porous-stabilized rare-earth barium copper oxide (REBCO) tape is an effective structure to solve a trade-off between the current-limiting and recovery performances of the resistive-type superconducting fault current limiters (RSFCLs). In the present study, a current-transfer-type porous-stabilized REBCO tape was proposed to suppress hot spots on the tape, which caused a recovery delay. In this type of REBCO tape, two porous stabilizers with different roles are utilized. The boiling heat transfer performance is improved with one of the porous stabilizers fixed with insulating epoxy on the tape while the current is transferred to the other porous stabilizer to decrease the Joule heating in the hot spot. To design the structure of the current-transfer-type porous-stabilized REBCO tape, the heat transfer performance with a porous medium and insulating epoxy was evaluated. The results indicated that there were suitable specifications for the porous medium and insulating epoxy for high heat transfer performance. The recovery performance of the current-transfer-type porous-stabilized REBCO tape was evaluated with the prototype using the selected porous stabilizer and insulating epoxy. The experimental results showed that the tolerable Joule heating was dramatically improved via current transfer to the porous stabilizer owing to the suppression of the temperature rise of the hot spot. The recovery time was shortened to 0.8 s. The present study showed one way to suppress the hot spots with a simple structure while maintaining the high electrical resistance of the REBCO tape.

Distributed generation adverse impact on the distribution networks protection and its mitigation.

Integration of Distributed Generation (DG) generates problems for the protection of Distribution Networks (DNs) in power systems. When DG is integrated into a power distribution system (DS), the radial nature of the network is altered and the power starts to flow in a reverse direction. In addition to the reverse flow of power, the DG upsurges the fault current level and affects the existing time intermission coordination of the protective overcurrent relay. This study proposes a reverse power relay (RPR) and Fault Current Limiter (FCL) to mitigate the fault current level and reverse power flow in a Distribution Network (DN) by the use of DG. The FCL works only as a unidirectional fault current limiter (UFCL) by restricting the flow of fault current that occurs in the main grid (MG) of the DG. However, FCLs can protect the flow of fault currents from the MG by affecting the operational flexibility and reliability of the DG. To overcome the flow of fault current of the DG, this study proposes RPR to monitor the power flow to the DG. Collectively the study focuses on the protection of radial DS by using RPR and UFCL. The analysis and the modeling were conducted on the 15KV DN of the radial feeder in Debre Markos DN. The 3Φ fault analysis (which is more severe than others) was performed to validate the protection capability of the mitigation techniques which were proposed in this study.

36-5-3] Stabilizer에 따른 2세대 고온 초전도 선재의 전기적 열화특성

2G High temperature superconducting(HTS) conductors are usually considered as appropriate superconductors for a superconducting coil to develop an applied superconducting apparatus such as a superconducting fault current limiter(SFCL), a superconducting cable, and a superconducting accelerator with high voltage or high ramping-up rate condition. The electrical degradation characteristics of HTS conductors due to electrical breakdown should be taken into consideration because high electric field intensity induced by high operating voltage or rapid ramping-up rate can affect the dielectric stability. In this study, the electrical degradation characteristics of 2G HTS conductors with different metal stabilizers made by SuNAM Co., Ltd. are analyzed and compared through dielectric experiments. As results, the most appropriate type of a 2G HTS conductor is recommended to manufacture superconducting apparatuses with a high voltage or rapid ramping-up rate condition.

Compensating Voltage Sag in Single Phase and Three Phase Lines Using Fault Current Limiter

Voltage sag compensation is provided on both sides of the Point of Common Coupling (PCC) by using FACTS Devices (STATCOM, APF, DSTATCOM, DVR, UPFC) and FCL. The FACTS dev ices provide compensation on input side and FCL provides compensation on output side. A sensitive load is considered at output side of PCC. This paper presents a component called Fault Current Limiter (FCL) in three phase lines. The main objective of the designed component is to protect the sensitive load from the shunt faults. The compensation is being provided at output side of PCC. Load voltage reduces upon the occurrence of shunt fault. The planned structure prevents voltage sag and counter balance the phase-angle of the PCC once fault prevalence. As a result, different feeders which are interlinked to the sub-station PCC can have attentive power quality. During this paper a high performance 3-phase fault current electrical model is planned. The analysis and design is carried out in MATLAB with SIMULINK.

Review on Compensating Voltage Sag in Single Phase and Three Phase Lines Using Fault Current Limiter

A high potential fault current levels in power grid is not a new approach, and should eventually exceed, the limitation of short-circuit-current would be existed protection devices. Different to pricey system upgrades of protection devices, Fault Current Limiters (FCL’s) gives an additional cost efficient solutions to forestall recent protection devices and different instrumentality on the system from being broken by excessive fault currents. Evaluation of short circuit faults may usually the origin of voltage sags at a purpose of common coupling point (PCC) during a power network, the extent of the voltage sag is proportional to the short current level, reducing the fault current level at intervals the networks will scale back voltage sags throughout faults and defend sensitive loads that are interfaced to a similar PCC. The planned structure prevents voltage sag and counter balance the phase-angle of the PCC once fault prevalence. As a result, different feeders which are interlinked to the sub-station PCC can have attentive power quality. During this paper a high performance 3-phase fault current electrical model is planned. A Matlab/Simulink model is developed and simulation results are conferred.

Coordination of adaptive virtual resistance controller and flux-coupling-type fault current limiter for LVRT fulfillment of virtual synchronous generator

The virtual synchronous generator (VSG) technology equips power inverters with virtual inertia and damping to access generation and storage more friendly. However, the VSG's weak performance to withstand fault current inrush and fulfill low-voltage ride-through (LVRT) operation should be carefully addressed. This paper presents an innovative method to coordinate adaptive virtual resistance controller (AVRC) and flux-coupling-type fault current limiter (FC-FCL). First, the theoretical modeling and transient characteristics of the VSG are illustrated. Then, the implementation of the coordinated AVRC and FC-FCL is done, with an elaboration of the coordination philosophy and the proposed approach's parameter design rules. Further, simulation validations are performed in MATLAB/Simulink. Different severities and types of faults are imitated, and the comparisons of the proposed method against the traditional VSG strategy, the single AVRC or FC-FCL, the inner current control, and the virtual voltage control are conducted. The results prove that: i) the proposed approach offers superior abilities to repress the fault current, alleviate the terminal voltage fluctuation and keep the VSG power balance. ii) the proposed approach can handle different severities and types of faults in the VSG. A satisfactory LVRT is obtained for the VSG with favorable frequency stability and power angle stability.

Lamination process of second generation high temperature superconducting tape at Shanghai Superconductor Technology

As the second generation high temperature superconducting (HTS) tape enters the stage of commercialization and mass production, it has been successfully applied in several power and magnet devices. Different application scenarios also put forward different requirements for the electrical and mechanical properties of the HTS tape. This paper focuses on introducing the post-processing treatments of HTS tape, primarily copper plating and lamination. By preparing typical samples, the properties of copper-plated tapes and laminated tapes have been experimentally compared. The results show that under the condition of sufficient liquid nitrogen flow, the steady-state over-current tolerance of copper-laminated tape is significantly better than that of stainless steel-laminated and copper-plated tapes. At the same room temperature resistance, the over-current impact tolerance of stainless steel-laminated tape is 2–3 times that of copper-plated tape; the maximum transient current beared by the tapes reached 3896 A when they were put under shock for 8 ms, which has significant advantages in the application of resistive fault current limiter. At 77 K, yield strength Rp0.2 of the three types of superconducting tapes are > 1100 MPa for stainless steel-laminated tape, 645–1037 MPa for copper-plated tape and < 500 MPa for copper-laminated tape. The critical tensile stress of stainless steel laminated-tape is higher than that of copper-plated tape and copper-laminated tape. The tape reinforced structure described in this paper can provide a helpful reference for future design and manufacture of superconducting applications in power and magnet industries.

Superconducting and non-superconducting fault current limiters: the developmental journey and upcoming prospects

ABSTRACT The energy hunger society drives for more electrical power consumption to raise the human conveniences have put tremendous pressure on the existing power system (PS) to function uninterruptedly. The continuous addition of non-linear loads brings a heavy inrush of fault current leading to transient instability in PS. To protect the PS and its precious elements, fault current limiters (FCLs) are generally installed with a view to limit those FCs before inviting severe damage and also quickly restore the PS to its original state. Furthermore, since faults are inevitable, efforts can only be made to minimise those damages by improving the FCLs. Herein, a brief history of FCLs, concepts, working principles, developmental stages, and experimental data, along with theoretical predictions, have been systematically presented. Finally, this article elaborates on the current challenges of FCLs, future perspectives, and, most importantly, their market potential.

Development of a Hybrid Fault Current Limiter Using Liquid Metal for Large Capacity MVdc Power Systems

A hybrid fault current limiter (FCL) for medium voltage direct current (MVDC) power systems is introduced in this paper. It achieves low operation loss and high current limiting resistance through the combination of a fast mechanical switch, a magnetic induction module and a number of liquid metal units (LMUs). Firstly, the parameters of the magnetic induction module are designed to achieve a desired fault current commutation process. Then, the working principle of LMU is introduced, and its resistance properties corresponding to the liquid metal arc are studied in detail. Equations are deduced to model the V-I characteristic of LMU. Thus the current limiting performance of the topology can be simulated. To verify the feasibility of the FCL, a 5-kV/5-kA prototype is developed and laboratory tests are implemented. Comparisons with other FCLs are also conducted to demonstrate the advantages of the proposed one. It is concluded that the prototype provides the basis for further commercial product development.

Air-Core-Transformer-Based Solid-State Fault-Current Limiter for Bidirectional HVdc Systems

Modular multilevel converter (MMC) high-voltage direct current (HVdc) transmission is a promising method to integrate renewable energies. However, limiting the dc-link fault current and accelerating the fault-current clearance are critical issues for MMC-HVdc systems. In this article, we propose an air-core-transformer-based fault-current limiter (ACT-FCL) in cooperation with the dc circuit breaker to limit fault-current rising and decrease fault-clearing time. Compared with the conventional dc reactor, hybrid current-limiting circuit, current-commutation-based fault-current limiter (FCL), and magnetic coupling FCL, the ACT-FCL can increase the equivalent inductance during the dc fault stage to reduce the rising rate and peak of fault current. The ACT-FCL can also decrease the equivalent inductance during the fault-current-clearing stage to reduce the fault-clearing time. The simulations and laboratory experiments verify the effectiveness of the proposed ACT-FCL in the bidirectional HVdc systems. The ACT-FCL may be extended to more fields, such as dc microgrid and domestic dc transmission.