Lightly Doped Drain MOSFETs Research Articles

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain (LDD) region and the built-in potential on MOSFETs, and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers. The model can predict the fringing-induced barrier lowering effect and the short channel effect. It is also valid for non-LDD MOSFETs. Based on this model, the relationship between threshold voltage roll-off and three parameters, channel length, drain voltage and gate dielectric permittivity, is investigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends slightly on channel length, drain voltage, and gate dielectric permittivity. The model is verified at the end of the paper.

Temporal and Spatial Current Stability of Smart Field Emission Arrays

Emission current stability and the spatial uniformity of field emission devices are improved when a lightly doped drain MOSFET (LD-MOSFET) is integrated with a field emission array (FEA). At comparable current levels, the emission noise (/spl Delta/I/I) decreased from 16.9% to 1.8%. Emission current fluctuation was reduced in the integrated device compared to the FEA device even in the presence of gases. Spatial current uniformity was achieved in the integrated MOSFET/FEA devices at different wafer positions and for different array sizes. The results are explained by a two-step field emission process, which consists of an electron supply step determined by the MOSFET inversion layer and an electron transmission step determined by the field emission barrier width. The device structure also results in low voltage control of emission current.

A compact I – V model for lightly-doped-drain MOSFETs

A novel model for lightly-doped-drain (LDD) MOSFETs is proposed, which utilizes the empirical hyperbolic tangent function to describe the I–V characteristics. The model includes the strong inversion and subthreshold mechanism and shows a good prediction for submicron LDD MOSFET. Moreover, the model requires low computation time consumption and is suitable for design of MOSFETs devices and circuits.

Novel Method of Intrinsic Characteristic Extraction in Lightly Doped Drain Metal Oxide Semiconductor Field Effect Transistors for Accurate Device Modeling

A lightly doped drain (LDD) region, particularly a gate-overlapped LDD (GOLD) region, is subjected to a gate electric field and its gate-controlled resistance affects the device characteristics. We developed a new extraction method for determining the intrinsic characteristics of LDD MOSFETs using a simple series resistance model, in which the GOLD region is assumed to be a depletion MOSFET with a negative threshold voltage derived from C–V measurement. Polycrystalline-silicon (poly-Si) TFTs with a channel length of 4–100 µm were used for the test LDD samples, particularly GOLD MOSFETs. It was demonstrated that the new proposed method precisely extracts the intrinsic characteristics of poly-Si GOLD TFTs by comparing them with the intrinsic characteristics of poly-Si Self-Aligned (SA) TFTs extracted by the conventional method.

Comparison of nanostructure LDD and EPI MOSFET

The technology for characteristic analysis of devices for high integration is changing rapidly. Therefore, to understand the characteristics of high-integrated devices by computer simulation and fabricate devices having such characteristics have become very important subjects. As devices become smaller from submicron to nanometer, we have investigated MOSFET built on an epitaxial layer (EPI) of a heavily doped ground plane by ISE-TCAD (technology computer aided design) to develop optimum device structure. We have analyzed and compared the EPI device characteristics such as impact ionization, electric field and I– V curve with those of a lightly doped drain (LDD) MOSFET. Also, we show that ISE-TCAD simulator is suitable for device simulation and discuss whether the scaling theory is suitable for nanostructure devices or not.

Forward gated-diode R-G current method: A simple novel technique for characterizing lateral lightly doping region of LDD MOSFET’s

This paper presents a simple novel technique-forward gated-diode R-G current method—to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N− MOSFET’s simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N− surface doping concentration and corresponding region’s interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET’s in the current ULSI technology.

Flicker noise modelling of small geometry LDD MOSFETs

An analytical 1/f noise model based on the evaluation of channel charge in small geometry Lightly Doped Drain (LDD) MOSFETs is developed. The analysis includes the short channel, narrow width, LDD and DIBL effects. The intricacy of analyses when both the device dimensions are scaled together has been overcome and a simple model valid in the submicrometer range is presented. It is found that the noise in small geometry LDD MOSFETs is higher than that in the short channel LDD MOSFETs putting hard limit to miniaturisation widthwise.

Low-frequency noise in proton damaged LDD MOSFET's

One of the concerns in the design of a guide camera for a satellite astronomy mission was an increase in the low-frequency noise in the output amplifier of the charge-coupled device (CCD) image sensor due to the radiation environment of the satellite. We investigated this potential problem by measuring the noise in several MOSFET's which had been subjected to varying amounts of high-energy proton radiation. These MOSFET's were typical of those used in the output stage of a CCD. They were lightly-doped drain (LDD) n-type buried-channel devices with aspect ratios between 4 and 6. We found a significant increase in the low-frequency noise of our devices after radiation. The frequency and temperature dependence of the noise indicates that it is generation-recombination noise due to the introduction of bulk trapping states. Fortunately, at the operating temperature of the CCD in the guide camera (-50/spl deg/C), the noise increase is very small in the frequency range of interest. However, at room temperature, the noise increase is large.

Cut off frequency and transit time analysis of lightly doped drain (LDD) MOSFETs

Analytical model for the transconductance, cut off frequency, transit time and fringing capacitance of LDD MOSFETs is presented with a simple approach. The analysis is carried out considering the LDD device as a conventional MOSFET with a series resistance [Z.-H. Liu et al., Threshold voltage model for submicrometer MOSFETs. IEEE Trans Electron Devices 1993; ED-40: 86–94] and a simple closed form expressions for cut off frequency and transit time is obtained. The total gate capacitance, i.e. the geometric and fringing capacitance, is calculated for both LDD and non-LDD devices and lower fringing capacitance is reported in LDD devices. Lower cut-off frequencies and higher transit time are reported in LDD devices for the same channel length.

A compact LDD MOSFET I-V model based on nonpinned surface potential

Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data.

An analytical model for the effect of graded gate oxide on the channel electric field in MOSFETs with lightly doped drain structure

A quasi-two-dimensional analytical model is developed to analyze the effect of process dependent Graded Gate Oxide (GGO) on the channel electric field in the drain region of an LDD (Lightly Doped Drain) MOSFET. The model takes GGO shape dependence, such as linear and parabolic shape, into consideration and the electric field profile obtained from the analysis shows that the maximum channel electric field ( E max) is varied with GGO length and GGO thickness. E max increases as the GGO thickness increases for relatively long GGO length, but for short GGO length, the contradictory phenomenon is observed. The dependence of the optimum LDD doping concentration for the minimum E max on the GGO length and GGO thickness is also investigated. With the same GGO dimensions, the dry reoxidation is less effective because of its linear shape of GGO, but has almost the same E max if it has the optimum LDD doping concentration. It is found that a GGO-LDD MOSFET must have short GGO length and thick GGO thickness as well as optimum LDD doping concentration in order to minimize the hot carrier induced degradation.

An effective channel length determination method for LDD MOSFETs

We propose a definition of MOSFET effective channel length (L/sub EFF/), that provides a method of determining L/sub EFF/ as a constant, and external resistance (R/sub EXT/) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L/sub EFF/ and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L/sub EFF/ is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L/sub EFF/ varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain.

Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors (MOSFETs) with Lightly Doped Drain Structure

We studied the effects of nitrogen implantation in the SiO2 sidewall spacer in detail in order to improve in the reliability of lightly doped drain (LDD) metal oxide field-effect transistors (MOSFETs), since the hot carrier degradation of LDD MOSFETs remains one of major issues even in the sub-quarter-micron region. It was found that nitrogen implantation in the SiO2 sidewall spacer can effectively suppress the hot carrier degradation of the LDD structure because the nitrogen atoms are segregated at the interface between the sidewall SiO2 and the Si substrate. This segregation can reduce the generation of interface states or electron traps in the sidewall spacer without causing gate depletion or an increase in gate resistance. Highly reliable sub-quarter-micron LDD N-MOSFETs can be realized using this nitrogen implantation technique.

Charge-pumping characteristics of virgin and stressed lightly-doped drain MOSFETs

Qualitative differences between the charge-pumping characteristics of lightly-doped drain (LDD) MOSFETs against the characteristics of conventional MOSFETs with abrupt junctions are analyzed and explained. The contribution of the particular interface regions in LDD devices to the charge-pumping characteristics is clarified by studying the spatial distributions of the charge-pumping threshold and flat-band voltages. A two-dimensional transient numerical model of the charge-pumping effect is also applied in the analysis. In order to understand the deep tail at the rising edge of the characteristics of LDD devices, an analytical model of the gate/LDD electrical-field fringing is derived. The accuracy of the analytical solution to the field-fringing problem is investigated regarding the self-induced lateral field in the semiconductor near the gate edge. The degradation of n-channel LDD MOSFETs under electrical stress is studied. The spatial distribution of stress-generated traps is extracted at different stress moments. Assuming these distributions as input the charge-pumping characteristics are calculated by employing the transient numerical model and compared with experimental data.

Enhanced hot-carrier-degradation in LDD MOSFET's under pulsed stress

Hot-carrier degradation of lightly doped drain (LDD) MOSFET's under ac stress is investigated. Enhanced ac degradation occurs in LDD MOSFET's as well as in single-drain MOSFET's. However, there is a peculiar degradation mechanism in LDD MOSFET's. For single-drain MOSFET's, enhanced ac degradation appears in both threshold voltage and transconductance at stress drain voltages larger than a critical value. On the other hand, for LDD MOSFET's, although the enhanced degradation in threshold voltage and transconductance appears at stress drain voltages larger than a critical value, the enhanced degradation in transconductance appears even under stress drain voltages lower than the critical value. The difference in the ac-enhanced degradation between LDD and single-drain structures can be explained by a hot hole generated neutral-electron-trap model and the change in hot-hole-injected oxide region according to stress bias conditions. >

Hot-carrier degradation of LDD MOSFET's with gate oxynitride grown in N/sub 2/O

Hot carrier immunity (HCI) of single drain (SD) and lightly doped drain (LDD) n-MOSFET's with gate oxide and N/sub 2/O gate oxynitride was compared. Gate oxynitride shows better HCI than gate oxide in SD devices but comparable in LDD devices. We show that oxide grown during the poly-silicon oxidation process after gate poly-silicon definition plays an important role in determining the hot carrier resistance of LDD n-MOSFET's with N/sub 2/O gate oxynitride. >

New pin MOSFET structure for hot carrier suppression

As an alternative to lightly doped drain (LDD) structures, a new pin MOSFET structure has been developed with near-intrinsic doping in the channel near the source/drain ends. This new structure has better hot carrier suppression, current drive capability and short channel effects compared to LDD MOSFETs.

Efficient semi-empirical I;- V model for submicron LDD MOS transistors

Abstract An efficient model is described for accurate prediction of the I- Vcharacteristics of submicron lightly-doped drain (LDD) MOSFETs down to an effective channel length of 0-65 μm (a mask channel length of 0-8 μm). It fully describes the l-V characteristics from the linear to the saturation operating region, with continuity in the drain current and its derivatives. All the parameters are extracted from experimentally measured l-V characteristics with preserved physical meanings. An improved effective mobility expression is proposed here to account for the series resistance in the n− region of LDD MOSFETs. A simple and accurate function of the drain and gate biasing voltages is also proposed for channel length modulation. This model supports the design of both nMOS and pMOS LDD FETs with any kind of channel or field implant. Comparisons between the measured and modelled l-V characteristics show excellent agreement for a wide range of channel lengths and biases.

The effect of fluorine on MOSFET channel length

The effect of fluorine on MOS device channel length has been evaluated. Fluorine has been introduced into the transistor by self-aligned ion implantation after the lightly doped drain (LDD) implant. The impact of fluorine in the LDD region, and its effect on the electrically determined channel length (L/sub eff/), has been examined. Measurements taken from 0.6- mu m LDD MOSFETs show a significant dependence of the L/sub eff/ on fluorine implant dose. The n/sup +/ resistor also shows more width reduction compared to unfluorinated samples. The decrease in channel length reduction by adding fluorine in the LDD region may yield way to relieve short-channel effects for the continuous scaling of CMOS devices into the deep-submicrometer region. >

Characteristics of profiled lightly-doped drain MOSFETs

Profiled lightly-doped drain (PLDD) MOSFETs are fabricated. Their characteristics are compared with those of other device structures. The current driving capability and transconductance of LDD devices can be increased with PLDD structures.