Lifting-based Discrete Wavelet Transform Research Articles

Design of hardware-efficient PVC recognition and classification system for early detection of sudden cardiac arrests

Sudden cardiac arrest (SCA) is a critical cardiovascular condition that needs greater emphasis on its early detection because it occurs unexpectedly and is fatal within minutes. Nowadays, wearable healthcare technologies are preferred for continuous monitoring of a wide range of cardiovascular diseases. Additionally, the recognition of cardiac arrhythmias such as premature ventricular contraction (PVC) and non-sustained ventricular tachycardia (NSVT) by wearable healthcare devices can help in the early detection of SCAs. The biggest challenge in this regard for compactly sized wearable healthcare devices is to design a hardware-efficient yet highly accurate PVC detection and classification system. In this work, a novel and hardware-efficient PVC recognition and classification system capable of categorizing PVCs into five types of ventricular arrhythmias, including NSVT, for the early detection of SCAs is proposed. For PVC detection, lifting-based discrete wavelet transform (LDWT) is used to perform pre-processing and extract morphological electrocardiogram (ECG) features and the Teager energy operator. When compared to the state-of-the-art ventricular arrhythmias and PVC detection systems, the proposed system performs PVC beat recognition and classification with an improved accuracy and sensitivity of 98.29% and 98.64%, respectively, while utilizing only 4.36% of the total resources when implemented on the Nexys 4 DDR FPGA board.

An Adaptive Binarization Method for Cost-efficient Document Image System in Wavelet Domain

Abstract In recent years, the preservation of handwritten historical documents and scripts archived by digitized images has been gradually emphasized. However, the selection of different thicknesses of the paper for printing or writing is likely to make the content of the back page seep into the front page. In order to solve this, a cost-efficient document image system is proposed. In this system, the authors use Adaptive Directional Lifting-Based Discrete Wavelet Transform to transform image data from spatial domain to frequency domain and perform on high and low frequencies, respectively. For low frequencies, the authors use local threshold to remove most background information. For high frequencies, they use modified Least Mean Square training algorithm to produce a unique weighted mask and perform convolution on original frequency, respectively. Afterward, Inverse Adaptive Directional Lifting-Based Discrete Wavelet Transform is performed to reconstruct the four subband images to a resulting image with original size. Finally, a global binarization method, Otsu’s method, is applied to transform a gray scale image to a binary image as the output result. The results show that the difference in operation time of this work between a personal computer (PC) and Raspberry Pi is little. Therefore, the proposed cost-efficient document image system which performed on Raspberry Pi embedded platform has the same performance and obtains the same results as those performed on a PC.

Lifting-based Discrete Wavelet Transform for Real-Time Signal Detection

Background: Discrete Wavelet Transform (DWT) is extensively useful in different Digital Signal Processing (DSP) applications. In this paper, Lifting scheme is introduced in three mother wavelets, which are Haar wavelet, Daubechies (db4) and Cohen-Daubechies-Feauveau (CDF) 9/7-tap wavelet also known as db9/7 wavelet. Method: In this work each of the architecture is compared with its Direct form. Haar wavelet is used to design the basic DWT architecture. Daubechies DWT (db4) orthogonal filters and Cohen-Daubechies-Feauveau (CDF) 9/7 bi-orthogonal wavelet filters are considered for DWT construction. Due to the uncomplicated design, lifting scheme provides less power consumption. Instead of set of filters, simple predict and update mechanism is introduced. The IEEE 754 floating point standard is used to represent the filter coefficients. The architectures are described in Verilog HDL and simulation is performed in Xilinx for FPGA implementation. All the architectures are synthesized in Cadence RC for 180 nm technology. Findings: The Lifting Scheme has 75-82% less power consumption and 27% area-efficiency than conventional DWT architectures. FPGA implementation is done using Altera Cyclone IV FPGA kit. Maximum operating frequency is 33.3MHz and 45MHz for 3-level and 1-level of decomposition respectively in DWT implementation. Conclusion: Due to the uncomplicated design, lifting scheme provides less power consumption. DWT designs are compared with respect to power consumption and area.

Evolutionary design of multiplierless lifting-based 2D DWT filters for low-resolution image processing

The most difficult challenge in developing a high-efficiency embedded image processing system relates to how to execute complicated Digital Signal Processing (DSP) algorithm with embedded processor, especially when processing high-resolution images. A whole system may start to run very slowly because of the large volumes of data being processed and the complexity of the algorithm, rendering it unable to achieve real-time processing. Executing motion detection in low-resolution image was already proved to be able to reduce the loading of data manipulation and to be able to help filter out noise and fake motion. However, smoothing filter pointed out in the work will affect the quality of image. Although the LL-band signal of a 2D Discrete Wavelet Transform (DWT) domain can retain the main part of the energy and information of the original image, a complex algorithm is more suitable for the application of a low-pass filter. Symmetric Mask-based DWT (SMDWT) has the advantage of reduced complexity, regular signal coding, and independent subband coding processing. In this paper, we use a Particle Swarm Optimization (PSO) approach to automatically evolve the multiplierless 2D SMDWT filters hardware architecture. The architecture employs only shift-and-addition operations to replace the complex floating-point multiplication and division operations. It can use shift-and-add based SMDWT filter to decompose a low-resolution image and do real-time image processing system design with low-resolution image processing technique.

A New VLSI Architecture for Symmetric Mask-Based Discrete Wavelet Transform

This work proposes a highly efficient VLSI architecture for 2-D dual-mode Symmetric Mask-based Discrete Wavelet Transform (SMDWT) to improve the critical issue of the 2-D Lifting-based Discrete Wavelet Transform (LDWT), and then obtains the benefit of lowlatency, reduced computing time, short critical path, and less transpose memory. The hardware architecture is based on the parallel and folding scheme to achieve higher shiftand- add based hardware utilization ratio and reduce the silicon area. Experimental results show that the transpose memory requirement of the N×N is 9N, the critical path is 1Ta, and the computing time is N^2/4. It is suitable for VLSI implementation and can be applied to real-time operating of computer vision applications.

Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform

Memory requirements (for storing intermediate signals) and critical path are essential issues for 2-D (or multidimensional) transforms. This paper presents new algorithms and hardware architectures to address the above issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the merits of low transpose memory (TM), low latency, and regular signal flow, making it suitable for very large-scale integration implementation. The TM requirement of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N×N</i> 2-D 5/3 mode LDWT and 2-D 9/7 mode LDWT are 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> and 4 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> , respectively. Comparison results indicate that the proposed hardware architecture has a lower lifting-based low TM size requirement than the previous architectures. As a result, it can be applied to real-time visual operations such as JPEG2000, motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding applications.

리프팅 기반 2차원 이산 웨이블렛 변환 필터의 효율적인 VLSI 구조

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an as-early-as-possible basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is .

Memory-efficient architecture of 2-D lifting-based discrete wavelet transform

This article presents new hardware architectures to address critical issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding modes) lifting-based discrete wavelet transform (LDWT) for Motion-JPEG2000. The massive requirement of transpose memory is the most critical for LDWT. The proposed architecture can support high-resolution videos and reduce the internal memory requirement significantly. In our LDWT approach, the signal flow is revised from row-wise only to mixed row- and column-wise, and a new architecture, called interlaced read scan architecture (IRSA), is used to reduce the transpose memory. By the IRSA approach, the transpose memory size is only 2N or 4N (5/3 or 9/7 mode) for an N × N DWT. Besides, the proposed 2-D LDWT operates with parallel and pipelined schemes to increase the operation speed. It can be applied to real-time visual operations such as JPEG2000 and Motion-JPEG2000.

Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines

A new discrete wavelet transform (DWT) architecture is proposed to realize a memory-efficient 2-D DWT processor. The proposed DWT processor conforms to dual-line scanning to remove the transpose buffer. In the previous single-line DWT architectures, the transpose buffer size is proportional to the row size of the image. The conventional dual-line DWT architecture is constructed by using the convolution-based filter structure and replicates registers to alternatively deal with two lines, resulting in a long delay, as well as a number of operators and registers. The proposed architecture is based on the lifting-based DWT to embed the additional registers in the middle of the DWT operation. In addition, the computation topology is optimized for the proposed dual-line DWT architecture to achieve almost the same hardware cost and critical path as the single-line DWT architecture.

Improved Low-Complexity Algorithm for 2-D Integer Lifting-Based Discrete Wavelet Transform Using Symmetric Mask-Based Scheme

Wavelet coding performs better than discrete cosine transform in visual processing. Moreover, it is scalable, which is important for modern video standards. The transpose memory requirement and operation speed are the two major concerns in 2-D lifting-based discrete wavelet transform (LDWT) implementation. This letter presents a novel algorithm, called 2-D symmetric mask-based discrete wavelet transform (SMDWT), to improve the critical issue of the 2-D LDWT, and then obtains the benefit of low-latency reduced complexity, and low transpose memory. The SMDWT also has the advantages of reduced complexity, regular signal coding, short critical path, reduced latency time, and independent subband coding processing. Furthermore, the 2-D LDWT performance can also be easily improved by exploiting an appropriate parallel method inherent to SMDWT. The proposed method has a significantly better lifting-based latency and complexity in 2-D DWT than normal 2-D 5/3 integer LDWT without degradation in image quality. The algorithm can be applied to real-time image/video applications.

Shape-Direction-Adaptive Lifting-Based Discrete Wavelet Transform for Arbitrarily Shaped Segments in Image Compression

In this paper, a new lifting-based shape-direction-adaptive discrete wavelet transform (SDA-DWT) which can be used for arbitrarily shaped segments is proposed. The SDA-DWT contains three major techniques: the lifting-based DWT, the adaptive directional technique, and the concept of object-based compression in MPEG-4. With SDA-DWT, the number of transformed coefficients is equal to the number of pixels in the arbitrarily shaped segment image, and the spatial correlation across subbands is well preserved. SDA-DWT also can locally adapt its filtering directions according to the texture orientations to improve energy compaction for images containing non-horizontal or non-vertical edge textures. SDA-DWT can be applied to any application that is wavelet based and the lifting technique provides much flexibility for hardware implementation. Experimental results show that, for still object images with rich orientation textures, SDA-DWT outperforms SA-DWT up to 5.88dB in PSNR under 2.15-bpp (bit/object pixel) condition, and reduces the bit-budget up to 28.5% for lossless compression. SDA-DWT also outperforms DA-DWT up to 5.44dB in PSNR under 3.28-bpp condition, and reduces the bit-budget up to 14.0%.

Efficient FPGA implementation of DWT and modified SPIHT for lossless image compression

In this paper, we present an implementation of the image compression technique set partitioning in hierarchical trees (SPIHT) in programmable hardware. The lifting based Discrete Wavelet Transform (DWT) architecture has been selected for exploiting the correlation among the image pixels. In addition, we provide a study on what storage elements are required for the wavelet coefficients. A modified SPIHT (Set Partitioning in Hierarchical Trees) algorithm is presented for encoding the wavelet coefficients. The modifications include a simplification of coefficient scanning process, use of a 1-D addressing method instead of the original 2-D arrangement for wavelet coefficients and a fixed memory allocation for the data lists instead of the dynamic allocation required in the original SPIHT. The proposed algorithm has been illustrated on both the 2-D Lena image and a 3-D MRI data set and is found to achieve appreciable compression with a high peak-signal-to-noise ratio (PSNR).

A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform"

A flipping structure for the discrete wavelet transform (DWT) was proposed by Huang et al., which aimed at shortening the critical path of the lifting-based one-dimensional (1-D) architecture and reducing the number of pipeline register used in 1-D architecture as well as the size of temporal buffer (TB) required in the line-based two-dimensional (2-D) architecture. In this paper, we explore the intrinsic relationship between the size of TB required in the line-based architecture for 2-D DWT (LBA2DDWT) and the number of registers used in a 1-D DWT module, and present a modified view on this issue that has been proposed by Huang et al. An improved method of mapping the registers used in 1-D DWT architecture to the TB required in LBA2DDWT is presented, which reduces more efficiently the size of memory required in LBA2DDWT than Huang's method. A parallel-based lifting scheme (PLS) for DWT and its VLSI architecture are presented. The proposed PLS of DWT not only reduces efficiently the critical path but also results in the equality of the forward discrete wavelet transform and inverse discrete wavelet transform implementations. Compared with Huang's method, the proposed PLS is more efficient in reducing critical path and/or the number of registers of VLSI implementation for 1-D DWT, and it can be concluded that the flipping structure of DWT is a special case of the PLS-based implementation.

A Survey on Lifting-based Discrete Wavelet Transform Architectures

In this paper, we review recent developments in VLSI architectures and algorithms for efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic principle behind the lifting based scheme is to decompose the finite impulse response (FIR) filters in wavelet transform into a finite sequence of simple filtering steps. Lifting based DWT implementations have many advantages, and have recently been proposed for the JPEG2000 standard for image compression. Consequently, this has become an area of active research and several architectures have been proposed in recent years. In this paper, we provide a survey of these architectures for both 1-dimensional and 2-dimensional DWT. The architectures are representative of many design styles and range from highly parallel architectures to DSP-based architectures to folded architectures. We provide a systematic derivation of these architectures along with an analysis of their hardware and timing complexities.

A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec

In this paper, we propose a high-performance and memory-efficient pipeline architecture which performs the one-level two-dimensional (2-D) discrete wavelet transform (DWT) in the 5/3 and 9/7 filters. In general, the internal memory size of 2-D architecture highly depends on the pipeline registers of one-dimensional (1-D) DWT. Based on the lifting-based DWT algorithm, the primitive data path is modified and an efficient pipeline architecture is derived to shorten the data path. Accordingly, under the same arithmetic resources, the 1-D DWT pipeline architecture can operate at a higher processing speed (up to 200 MHz in 0.25-/spl mu/m technology) than other pipelined architectures with direct implementation. The proposed 2-D DWT architecture is composed of two 1-D processors (column and row processors). Based on the modified algorithm, the row processor can partially execute each row-wise transform with only two column-processed data. Thus, the pipeline registers of 1-D architecture do not fully turn into the internal memory of 2-D DWT. For an N/spl times/M image, only 3.5N internal memory is required for the 5/3 filter, and 5.5N is required for the 9/7 filter to perform the one-level 2-D DWT decomposition with the critical path of one multiplier delay (i.e., N and M indicate the height and width of an image). The pipeline data path is regular and practicable. Finally, the proposed architecture implements the 5/3 and 9/7 filters by cascading the three key components.

Classification of EEG signals using neural network and logistic regression

Epileptic seizures are manifestations of epilepsy. Careful analyses of the electroencephalograph (EEG) records can provide valuable insight and improved understanding of the mechanisms causing epileptic disorders. The detection of epileptiform discharges in the EEG is an important component in the diagnosis of epilepsy. As EEG signals are non-stationary, the conventional method of frequency analysis is not highly successful in diagnostic classification. This paper deals with a novel method of analysis of EEG signals using wavelet transform and classification using artificial neural network (ANN) and logistic regression (LR). Wavelet transform is particularly effective for representing various aspects of non-stationary signals such as trends, discontinuities and repeated patterns where other signal processing approaches fail or are not as effective. Through wavelet decomposition of the EEG records, transient features are accurately captured and localized in both time and frequency context. In epileptic seizure classification we used lifting-based discrete wavelet transform (LBDWT) as a preprocessing method to increase the computational speed. The proposed algorithm reduces the computational load of those algorithms that were based on classical wavelet transform (CWT). In this study, we introduce two fundamentally different approaches for designing classification models (classifiers) the traditional statistical method based on logistic regression and the emerging computationally powerful techniques based on ANN. Logistic regression as well as multilayer perceptron neural network (MLPNN) based classifiers were developed and compared in relation to their accuracy in classification of EEG signals. In these methods we used LBDWT coefficients of EEG signals as an input to classification system with two discrete outputs: epileptic seizure or non-epileptic seizure. By identifying features in the signal we want to provide an automatic system that will support a physician in the diagnosing process. By applying LBDWT in connection with MLPNN, we obtained novel and reliable classifier architecture. The comparisons between the developed classifiers were primarily based on analysis of the receiver operating characteristic (ROC) curves as well as a number of scalar performance measures pertaining to the classification. The MLPNN based classifier outperformed the LR based counterpart. Within the same group, the MLPNN based classifier was more accurate than the LR based classifier.

A High-Performance and Memory-Efficient Pipeline Architecture for the 5/3 and 9/7 Discrete wavelet Transform of JPEG2000 Codec

In this paper, we propose a high-performance and memory-efficient pipeline architecture which performs the one-level two-dimensional (2-D) discrete wavelet transform (DWT) in the 5/3 and 9/7 filters. In general, the internal memory size of 2-D architecture highly depends on the pipeline registers of one-dimensional (1-D) DWT. Based on the lifting-based DWT algorithm, the primitive data path is modified and an efficient pipeline architecture is derived to shorten the data path. Accordingly, under the same arithmetic resources, the 1-D DWT pipeline architecture can operate at a higher processing speed (up to 200 MHz in 0.25-/spl mu/m technology) than other pipelined architectures with direct implementation. The proposed 2-D DWT architecture is composed of two 1-D processors (column and row processors). Based on the modified algorithm, the row processor can partially execute each row-wise transform with only two column-processed data. Thus, the pipeline registers of 1-D architecture do not fully turn into the internal memory of 2-D DWT. For an N/spl times/M image, only 3.5N internal memory is required for the 5/3 filter, and 5.5N is required for the 9/7 filter to perform the one-level 2-D DWT decomposition with the critical path of one multiplier delay (i.e., N and M indicate the height and width of an image). The pipeline data path is regular and practicable. Finally, the proposed architecture implements the 5/3 and 9/7 filters by cascading the three key components.

Efficient Architectures for 1-D and 2-D Lifting-Based Wavelet Transforms

The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures.

Low power embedded extension algorithm for lifting-based discrete wavelet transform in JPEG2000

A novel algorithmic technique for reducing power and area consumption of the discrete wavelet transform (DWT) on CMOS-based DSP architectures is presented. The technique reduces power by combining the data-extension procedure into the lifting-based DWT core. It is demonstrated that the new algorithm can be used to obtain more than 50% reduction in the amount of memory required, leading to significant reduction in area and power.