A New VLSI Architecture for Symmetric Mask-Based Discrete Wavelet Transform

Abstract

This work proposes a highly efficient VLSI architecture for 2-D dual-mode Symmetric Mask-based Discrete Wavelet Transform (SMDWT) to improve the critical issue of the 2-D Lifting-based Discrete Wavelet Transform (LDWT), and then obtains the benefit of lowlatency, reduced computing time, short critical path, and less transpose memory. The hardware architecture is based on the parallel and folding scheme to achieve higher shiftand- add based hardware utilization ratio and reduce the silicon area. Experimental results show that the transpose memory requirement of the N×N is 9N, the critical path is 1Ta, and the computing time is N^2/4. It is suitable for VLSI implementation and can be applied to real-time operating of computer vision applications.