An efficient VLSI architecture for discrete wavelet transform

Abstract

A Lifting-based Discrete Wavelet Transform (DWT) is a time/frequency analysis conversion method that is often used in JPEG2000 image compression systems. Its filter bank has a dual-mode base function that consists of coefficients of 9/7 and 5/3. Generally, in the process of realizing Very Large Scale Integration (VLSI) architecture, there is a longer critical paths and increased cost of hardware, so paper proposes a folding and pipelined architecture to solve the problems in VLSI architecture design; In order to solve the problem of a large area of hardware due to the excessive use of the multipliers in dual-mode operation, a shifter-adder-multiplier architecture and dual-mode filter architecture are combined. The experimental results show that the hardware architecture proposed in this work has a short critical path. The hardware supports dual-mode hardware wavelet coefficients, decrease latency, and multiplierless, and more suitable for VLSI to implement and apply in low cost JPEG2000 compression systems.