LFSR Reseeding Research Articles

Efficient Test Sequence Generator for Area Optimization in LFSR Reseeding

In this paper, a new concept of test pattern generator is used with Seed Initialization Method (SIM) for area optimization in LFSR reseeding. LFSR Reseeding is the method which is mainly used in logic BIST. Some of the reseeding mechanism needs some sort of memory to store all seeds. But this issue is overcome by present method. By this method, the proposed test pattern generator employs the output response of the CUT to the LFSR as the controlling signal to transform the LFSR state. It contains a net providing cell and LFSR with reversal logic to conform that there is no storage of seeds. When compared to previous methods, by using this approach (SIM), the test sequence that will have been given to LFSR is much reducing. The empirical outcome on ISCAS circuits shows that the conferred seed initialization method has brought reduced area overhead.

A LFSR Reseeding Scheme Based on Division by 2 to the Power of Integer

As the number of specified bits of different test patterns varies widely in a deterministic test cube, all test patterns are concatenated to a data flow. The original test data can be re-divided by 2 to the power of integer according to the successful characteristics of the LFSR coding, whose length equals to the power of 2 in every division. In the new test approach, the numbers of specific bits in the new test vectors are very close. Hence the encoding efficiency can be enhanced in the process of LFSR. And experimental results show that the compression ratio of this scheme can improve 2.32 % than that of hybrid coding. Compared with the previous schemes, the proposed scheme can increase the encoding efficiency with simple decompression structure and less area overhead.

LFSR reseeding method based on dividing test cubes by equal number of specified bits

LFSR reseeding method based on dividing test cubes by equal number of specified bits

Dual multiple-polynomial LFSR for low-power mixed-mode BIST

Mixed-mode BIST offers complete fault coverage with short test application times and small test data requirements. Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. Several techniques have been recently proposed for reducing power dissipation during BIST. The work presented addresses the problem of reducing power dissipation in mixed-mode BIST. A new mixed-mode test pattern generator is proposed with reduced power dissipation during test when compared with existing test pattern generators. This is achieved by combining the masking properties of AND/OR composition with LFSR reseeding. Extensive experiments were performed on several benchmark circuits using commercial synthesis and simulation tools to validate the efficiency and assess the overhead of the proposed solution. Experimental results show that reductions up to 20% in average power dissipation during test can be achieved when compared with traditional test pattern generators.