Efficient Test Sequence Generator for Area Optimization in LFSR Reseeding

Abstract

In this paper, a new concept of test pattern generator is used with Seed Initialization Method (SIM) for area optimization in LFSR reseeding. LFSR Reseeding is the method which is mainly used in logic BIST. Some of the reseeding mechanism needs some sort of memory to store all seeds. But this issue is overcome by present method. By this method, the proposed test pattern generator employs the output response of the CUT to the LFSR as the controlling signal to transform the LFSR state. It contains a net providing cell and LFSR with reversal logic to conform that there is no storage of seeds. When compared to previous methods, by using this approach (SIM), the test sequence that will have been given to LFSR is much reducing. The empirical outcome on ISCAS circuits shows that the conferred seed initialization method has brought reduced area overhead.