A methodology for LBIST logic diagnosis in high volume manufacturing

Abstract

LBIST (Logic Built-In Self Test) is a structural test method that tests a circuit by running test patterns generated on the die as opposed to ATPG (Automatic Test Pattern Generation) method in which the test patterns are pre-generated to test specific fault types. LBIST has emerged as an alternative scan based test methodology due to its attractive benefits such as reduced pattern size and field testability. LBIST uses pseudo random patterns enabling it to generate patterns on the die saving tester memory to a large extent. At the same time it poses challenges to enable fail data collection for later debug as the LBIST test iterations are usually large (typically 100000). Tester time is not a big concern for a LBIST based method if the objective is to know if the unit passed or failed, but memory usage is a concern due to the need to compare intermediate scan responses to determine and collect failing responses for diagnosis and debug purposes. This motivated us to come up with a methodology for fail data collection that optimizes tester time and memory and collects enough fail data to provide acceptable diagnosis quality. In this paper we have presented a methodology for fail data collection and discussed the tester overheads for LBIST logic diagnosis.