An effort-minimized logic BIST implementation method

Abstract

This paper presents LBIST (Logic Built-In Self Test) design practice at Cisco Systems. It focuses on the LBIST design tasks that could affect design schedules and efforts. These are design timing closure and signature mismatch debugging. Our timing closure technique guarantees timing closure for LBIST insertion without any iteration between synthesis and LBIST insertion. In addition, it guarantees that only one iteration between static timing analysis and LBIST insertion is required to close all timing violations. The signature mismatch debugging technique effectively identifies the causes by indicating the pattern, the scan flip-flop and its operation mode, where the mismatch happens. These techniques save design efforts and the product-to-market time. We have integrated this method into an ASIC design flow. The results of using this flow in a large telecommunication design are described.