Output Voltage Levels Research Articles

Design and Performance Comparison of Effect of Different Switching Sources on Thermoelectric Energy Harvesting Using Single-Inductor Boost Converters

This paper presents a comparison for the amount of power generated using different switching sources in a DC-DC boost converter designed to generate 3-5 V output voltage. The desired output voltage is sufficient to charge a rechargeable battery. The input voltage is supplied by a commercially available thermoelectric generator module (TEG) when subjected to appropriate temperature gradient. Three boost converter circuit configurations with gate pulse, square wave, and PWM switching sources are designed to step-up the low DC voltage of 0.2 V from thermoelectric energy harvester. The output voltage and current levels are measured for estimating the amount of increase in output power. Gate pulsed switching in boost converter generated a highest output voltage of 5.26 V, while square wave triggered circuit could generate maximum 3.5 V. PWM based switching generated an output voltage of 1.98 V for input supply of 0.2 V.

Model Simulasi Interleaved DC-DC Flyback Untuk Dual Stage Micro-Inverter

DC-DC converter is one of the important parts in the micro-inverter which is used in photovoltaic applications. Its function is to change the output voltage level of 48 Vdc to 5 V dc. The proposed converter topology is flyback because the number of components used is simple so it can reduce production costs and improve ripple voltage. In the flyback converter simulation modeling is done in interleaved mode with maximum output power 12 W using Ltspice software. From the simulation results, it is found that by applying a switching frequency 100 kHz, the value of the primary inductor (Lp) 20 µH, secondary inductor (Ls) 1.5µH, output capacitor (Cout) 100 uF, ripple voltage (VR) 81.02 mV and using IC LT 3758.

High‐Gain Logic Inverters based on Multiple Screen‐Printed Organic Electrochemical Transistors

AbstractOrganic electronic circuits based on organic electrochemical transistors (OECTs) are attracting great attention due to their printability, flexibility, and low voltage operation. Inverters are the building blocks of digital logic circuits (e.g., NAND gates) and analog circuits (e.g., amplifiers). However, utilizing OECTs in electronic logic circuits is challenging due to the resulting low voltage gain and low output voltage levels. Hence, inverters capable of operating at relatively low supply voltages, yet offering high voltage gain and larger output voltage windows than the respective input voltage window are desired. Herein, inverters realized from poly(3,4‐ethylenedioxythiophene):polystyrene sulfonate‐based OECTs are designed and explored, resulting in logic inverters exhibiting high voltage gains, enlarged output voltage windows, and tunable switching points. The inverter designs are based on multiple screen‐printed OECTs and a resistor ladder, where one OECT is the driving transistor while one or two additional OECTs are used as variable resistors in the resistor ladder. The inverters’ performances are investigated in terms of voltage gain, output voltage levels, and switching point. Inverters, operating at +/−2.5 V supply voltage and an input voltage window of 1 V, that can achieve an output voltage window with ∼110% increment and a voltage gain up to 42 are demonstrated.

Improved modified a multi-level inverter with a minimum total harmonic distortion

Renewable energy sources are developed as a result of the increased demand for electrical power. The nature of the solar energy source is DC. The DC source for many applications needs to be converted to AC. The inverter is used to convert the power from DC to AC. Total harmonic distortion (THD) is a significant concern with inverters. Multi-level inverters are used to reduce the THD. The stair output voltage of the multi-level inverter not only reduces the THD but also reduces the switches' stresses, so a low voltage rating can be used for the switches. In this paper, a modified inverter topology is introduced in which the number of switches is reduced for the same number of output voltage levels, which leads to reducing the losses and the cost. To reduce the THD, different amplitudes for the carrier signals that control the switches in each level are suggested. Another method to reduce the THD by using different capacitor values across the input DC source is presented. The MATLAB/Simulink is used to show the validity of the suggested modified topology and the modifications.

Switching Sequence Control 31-Level Asymmetric Cascaded of Reduced Switch Count Multilevel Inverter with Multi Carrier Pulse Width Modulation

Various pulse width modulation techniques, including as cascaded multilevel inverters (MLI), diode clamped multilevel inverters, and flying capacitor multilevel inverters, can be used to simply operate common inverters. Due to increased switching losses, current MLIs cannot reach high efficiency. Due to lower losses and THD than standard MLI topologies, the asymmetric cascaded multi-level H-bridge inverter architecture examined in this white paper employs fewer switches and more output voltage levels (Total Harmonic Distortion). The THD is less than the IEEE standard because of the suggested architecture. In this instance, phase difference (PD) multi-carrier PWM techniques are used to control the gate pulses using sinusoidal reference. Each switch receives a different pulse pattern thanks to a method of decimal-to-binary conversion. It is possible to utilise the suggested circuit for applications requiring moderate to high power, and it is quite simple to evaluate. Utilize the MATLAB/SIMULINK environment to simulate time-domain behaviour for the 31-level and 33-level multilevel inverter topologies.

Design of Voltage Level Shifter Using CNTFET and Analysis of Process Voltage Temperature Variation

In this work, we have presented the design of voltage level shifter using carbon nanotube field effect transistors (CNTFETs). The proposed design is capable of converting two input voltage levels to two output voltage levels. The threshold voltage of CNTFETs is suitably chosen to achieve the desired output. The proposed design can perform both up and down shifting which is very useful in the system-on-a-chip design to interface with other peripherals. It exhibits lower delay and power delay product in comparison with the existing complementary metal–oxide–semiconductor-based voltage level shifters. The proposed circuit is very effective as it eliminates the requirement of additional voltage level shifter for designing systems with multi-power supply voltage domain in the nanoscale regime. The design has been analyzed for different process, voltage and temperature corners. It has been shown that the design works perfectly with [Formula: see text] variation in the diameter of the carbon nanotubes used in the CNTFET. The performance varies slightly with [Formula: see text] variation in operating voltage. Our analysis shows that the design is thermally stable for a wide variation in operating temperature.

A non‐isolated high step‐up MIMO DC–DC converter for renewable energy applications

This article offers a non-isolated DC–DC converter with dual-ports for input and dual-ports for output with high step-up ability. The converter has different levels of output voltage. The benefits of the proposed topology consist of the capability of giving high voltage gains with low duty cycle amount, the simple control of each duty cycle, and low per-unit peak voltage stress (PPVS) over the semiconductors. The presented structure is suitable for clean energy applications. The operation principles, steady-state analysis, voltage, and current equations extraction in continuous conduction mode (CCM) are carried out. To confirm the superiority of the proposed topology, the efficiency of the converter is compared to other multi-input (MI) and multi-output (MO) converters which were recently published in the literature. Eventually, an implemented prototype in the laboratory is used to verify the performance of the proposed structure.

The Main objective of this project is to develop a power management system that will control the power flow and energy demand of an integrated renewable energy system with the focus on solar energy and wind energy. These storage systems are needed to provide high reliability and control systems are necessary for the stable and optimal operation of the whole

A new multilayer inverter topology is proposed in this study. The cascaded feature is used in this innovative topology. In addition to the isolated DC sources seen in Cascaded H-bridge. The clamping diode in Diode and the multilevel inverter (CHB-MLI) Inverter with Clamped Multilevel (DC-MLI). With these advantages, an inverter topology with 18 total component counts when coupled had been discovered. This proposed topology has the potential to generate up to According to the ratio allocated to its DC sources, there are 17 output levels. Aside from increasing the number of output voltage levels, this study has a relatively low number of component counts. The THD limit defined by IEEE standard is also a goal (i.e. 5 percent) all voltage applications under 69kV.To ensure that the suggested topology is functional, it is being simulated in Matlab/Simulink with various modulation indexes. The amount of THD, the number of voltage outputs, and the RMS voltage are all being monitored and discussed. Finally, to assess the uniqueness of the suggested topology, a comparison study with recently disclosed topologies is being carried out.

Design and implementation of reduced number of switches for new multilevel inverter topology without zero-level state

<p>Currently, multilevel inverter (MLI) has been chosen over conventional inverter because of less harmonic distortions and higher output voltage levels. In this paper, 15 level inverter with reduced number of power switching devices is designed. Different output voltage levels can be obtained including zero level or with none zero level (NoneZero level). Single phase MLI inverter with 7 switches is built, simulated, and implemented practically. The system depending on modified absolute sinusoidal pulse width modulation (MASPWM) controller strategy is adopted. Simulation results clarified that MLI with NoneZero level provides output voltage with total harmonic distortion (THD) percent less than with zero level. The THD of the 15 level output voltage with zero level is 3.39%, while with NoneZero level is 3%, respectively. The system is tested at different output levels. The THD values at different output voltage levels is reduced by 12% depending on NoneZero level state. Depending on what has been achieved, the system has been implemented practically with NoneZero<br />level and the THD value was 3.1%. These results prove the success of the suggested MLI circuit and MASPWM controller to obtain the required voltage level and THD.</p>

Nine-level inverter with lesser number of power semiconductor switches using dSPACE

In this paper, a single-phase nine-level multilevel inverter (MLI) topology is created in which reduced number of switches, diodes and gate driver circuits can be used so as to obtain higher output voltage levels. Due to this configuration, the blocking voltage value across the switches will also get reduced. In this proposed single-phase MLI topology, increase in output voltage levels can be observed whenever there is increment in the number of switches in the configuration. Proper mathematical modeling and analysis of the voltage waveform of the proposed inverter have been done for a 9-level MLI. MATLAB platform is used for modeling and simulation of the MLI. Modulation index is varied in order to observe various outcomes through simulation. The proposed nine-level inverter configuration is experimentally evaluated in the laboratory for various modulation indices so as to validate the simulation results. Comparison of this topology is done with the classical MLIs in order to illustrate its advantages.

Maximum resolution of switched capacitor converter: a graphical approach

The efficiency of a switched capacitor converter can be represented as the ratio of the output voltage to open-circuit voltage. Switched capacitor converters with adjustable gain are designed with multiple no-load voltages to obtain higher efficiency over the voltage control range. This paper aims to realize the maximum resolution of a switched capacitor converter. A graphical representation of the output voltages formation has been proposed. The voltage composition diagram reveals a switching pattern of the multiphase operation cycle that leads to the desired output voltage. The proposed method has been applied to determine all possible output voltage levels that lead to maximum resolution. A three-capacitor converter has been controlled with the proposed scheme. The simulation results show that the output voltage follows the reference voltage closely. The converter provides 60% more output voltage steps compared to the nearest comparable design in the literature.

A new tri-source symmetric cascaded multilevel inverter topology with reduced power components

PurposeMultilevel inverters become very popular in medium voltage applications owing to their inherent capability of reconciling stepped voltage waveform with reduced harmonic distortion and electromagnetic interference. They have several disadvantages like more number of switching devices required and devices with high voltage blocking and need additional dc sources count to engender particular voltage. So this paper aims to propose a novel tri-source symmetric cascaded multilevel inverter topology with reduced number of switching components and dc sources.Design/methodology/approachA novel multilevel inverter has been suggested in this study, offering minimal switch count in the conduction channel for the desired voltage level under symmetric and asymmetric configurations. This novel topology is optimized to prompt enormous output voltage levels by employing constant power switches count and/or dc sources of voltage. The topology claims its advantages in generating higher voltage levels with lesser number of voltage sources, gate drivers and dc voltage sources.FindingsThe consummation of the proposed arrangement is verified in Matlab/Simulink R2015b, and an experimental prototype for 7-level, 13-level, 21-level, 29-level, 25-level and 49-level operation modes is constructed to validate the simulation results.Originality/valueThe proposed topology operated with six new algorithms for asymmetrical configuration to propel increased number of voltage levels with reduced power components.

A comprehensive design approach for a three‐winding planar transformer

In this paper, a new three-winding planar transformer design with the integrated leakage inductor is proposed for a triple-active-bridge converter. It enables two output voltage levels: a high voltage (HV) output port and a low voltage (LV) output port. The primary and secondary windings are split unevenly in both side legs while the tertiary winding is connected in parallel. The unique winding configuration enables: (i) enhanced efficiency with low volume; and (ii) suppressed parasitic capacitances. Detailed transformer reluctance and loss models are developed in the design process. The core geometry is optimized using a reluctance-model-based mathematical computation. Moreover, comprehensive high-fidelity simulations are conducted to analyse the trade-offs among parasitic capacitances, losses, and inductances. The customized core and the non-overlapping winding boards are assembled, characterized, and tested under various power flow conditions.

An Improved Conventional Diode-Clamped Multilevel Inverter Using Non-Zero Triangular- Based Unipolar Modulation Scheme

This paper presents an improved conventional diode-clamped multilevel inverter using non-zero triangular-based unipolar modulation scheme. The proposed scheme is meant to reduce the number of carrier waves, minimize the circuits of modulation scheme and obtain stabilized output voltage waveforms. Non-zero triangular-based unipolar modulation scheme is actualized by using two zero-free triangular wave carriers and two modulating sinewaves for line-to- line five level output voltage waveforms in single phase full bridge diode-clamped multilevel inverter unlike conventional multicarrier sinusoidal pulse width modulation that uses four triangular waves and one modulating sinewave for the same inverter type. The proposed system also used microcontroller in the combinational of its wave signals in order to generate the appropriate triggering signals for switching the power semiconductor switches. The proposed system has the following features: (i) It produces two distinct triggering trains (W1 and W2) meant to reduce the low and high harmonics unlike conventional modulation techniques (ii) All its carrier waves operate in continuous current mode which makes it unique from other multicarrier and other related modulation schemes (iii) it has low component counts. The proposed scheme on the conventional diode-clamped inverter produced the following results: voltage and current with total harmonic distortions of 0.4547%, stabilized 400V output voltage and 20A output current, probability results at each level of voltage and current occurrences are 0.10, 0.25, 0.25, 0.75 and 0.90; power output of 80kW, low component counts of modulation circuit scheme and experimental prototype.

High-Precision Low-Temperature Drift LDO Regulator Tailored for Time-Domain Temperature Sensors.

This paper proposes a high-precision LDO with low-temperature drift suitable for sensitive time-domain temperature sensors. Its topology is based on multiple feedback loops and a novel approach to frequency compensation, that allows the LDO to maintain a large DC gain while handling capacitive loads that vary over a wide range. The key design constraints are derived by using a simplified, yet intuitive and effective, small-signal analysis devised for LDOs with multiple feedback loops. Simulation and measurement results are presented for implementation in a standard 130 nm CMOS process: the LDO outputs a stable 1 V voltage, when the input voltage varies between 1.25 V to 1.5 V, the load current between 0 and 100 mA, and the load capacitor between zero and 400 pF. It exhibits a DC load regulation of 1 µV/mA, a 288 µV output offset with a standard deviation of 9.5 mV. A key feature for the envisaged application is the very low thermal drift of the output offset: only 14.4 mV across the temperature range of −40 °C to +150 °C. Overall, the LDO output voltage stays within +/−3.5% of the nominal DC value over the entire line voltage, load, and temperature ranges, without trimming. The LDO requires only 1.4µA quiescent current, yet it provides excellent responses to load transients. The output voltage undershoot and overshoot caused by the load current jumping between 0 and 100 mA in 1 µs are: 10%/22% for CL = 0 and 12%/16% for CL = 400 pF, respectively. A comparative analysis against seven LDOs published in the last decade, designed for similar levels of supply voltage and output voltage and current, shows that the LDO presented here is the best option for supplying sensitive time-domain temperature sensors. The smallest thermal drift of the output offset, smaller than +/−15 mV, that is, 6.7 times smaller than its closest competitor, and the best overall performance when PSR up to 1 kHz, was considered.

An electro-optical system for improving graphene nanopore DNA Sequencing

I propose a new electro-optical system for sequencing single-stranded DNA molecules. The localized plasmons in graphene combined with the nanopore-based DNA translocation have been suggested for sequencing DNA molecules and decreasing the translocation speed. These localized surface plasmon resonances in the graphene nanopore have three dominant modes. Every-mode peak wavelength is shifted while the DNA nucleobases are presented to the nanopore. The ultraviolet photodiodes with narrow-band filters can separate each mode individually. Then, the electrical-current to voltage convertor, differential pairs based on the bipolar transistors, combine all modes in the effective output voltage. The output voltage level of the circuit is sensitive to the DNA presence and is unique for each DNA nucleobase. Analyzes have been performed for different central wavelengths and spectral width of the light source. Results show that the best sensitivity to the DNA molecule is 6.04, and the best selectivity is 1.1. These factors are directly related to the method's applicability for DNA translocation sensing and DNA sequencing; they are enormously improved. The proposed method and results shed light on a higher selectivity for DNA nucleobases which is the main bottleneck for nanopore DNA sequencing.

Model Predictive Control Scheme of a Four-Level Quasi-Nested Converter Fed AC-Drive, with dc-Link Voltage-Drift Compensation

In this paper, a Model Predictive Control (MPC) strategy is introduced for its application in a four-level quasi-nested topology, feeding an Interior Permanent Magnet Synchronous Machine (IPMSM) AC-drive. The proposed control strategy is capable to synthesize the required output space vectors to ensure perfect tracking of the AC-drive speed reference under different loading conditions, while also ensuring voltage balance between the dc-link capacitors. The proposed converter topology is based on a reduced number of components compared to other mature converter topologies, such as the neutral-point clamped converter (NPC) or the active neutral-point clamped converter (ANPC) topologies, when compared in terms of the number of output voltage levels, since this quasi-nested topology does not require passive clamping devices such as diodes or active switches. Moreover, no floating dc-link capacitors with asymmetrical voltage levels are employed, thus simplifying the dc-link capacitor voltage balance mechanism. This work presents the switching operation principles and MPC control law when supplying an IPMSM AC-drive load are addressed in detail. Simulation and validation results using a Hardware in the Loop (HIL) prototype under different operation conditions are presented in order to validate the proposed converter topology and control strategy.

Effects of Random Switching Schemes on the EMI Levels of Conventional and Interleaved Buck Converters for Mobile Devices

This study presents a comprehensive detailed analysis of the effect of five different random modulation switching schemes and their randomness levels on the elector magnetic interference (EMI) of designed simple and interleaved DC-DC buck converters for smartphone applications. The analyzed switching schemes are pulse width modulation (PWM), random pulse width modulation (RPWM), random pulse position modulation (RPPM), random carrier frequency modulation various duty (RCFMVD), and random carrier frequency modulation fixed duty (RCFMFD). The experimental analysis is performed for all aforementioned switching modulation schemes at the switching frequency of 20 kHz and different randomness levels (RL) (30% to 85%). For a fixed RL of 40%, the switching current harmonics/conducted emission (CE) levels are 5–10 dB/11 dBμV and 17 dB/14 dBμV lower for the RCFMVD case when compared to conventional PWM for both simple and interleaved buck-converters, respectively. The observed switching current harmonics and CE levels for interleaved schemes are around 23 dB and 12 dBμV lower when compared to the conventional simple buck converter scheme for the analyzed circuit configurations. The EMI levels decrease with the increase in the randomness levels from 30% to 85% with less variations in the output voltage level. The findings suggest that a interleaved buck converter circuit with the least-independent switching mechanisms and higher randomness is more appropriate for the reduction of both current spikes and CE levels with RCFMFD as the switching modulation scheme.

Aquila Optimization Based Harmonic Elimination in a Modified H-Bridge Inverter

Multilevel inverters (MLIs) are capable of producing high-quality output voltage and handling large amounts of power. This reduces the size of the filter while also simplifying the circuitry. As a result, they have a wide range of applications in industries, particularly in smart grids. The input voltage boosting feature is required to use the MLI with renewable energy. Moreover, many components are required to get higher output voltage levels that add weight and cost to the circuit. Numerous MLI topologies have been identified to minimize the losses, device count, and device ratings. A seven-level modified H-bridge inverter with a reduced component count, and reduced THD is presented in this paper. Two DC sources with six IGBTs have been used to generate a seven-level output voltage, and the Aquila Optimizer (AO) has been implemented to get the regulated output. MATLAB/Simulink environment has been used for designing the simulation model. Furthermore, the simulation result has been validated in the laboratory on a hardware setup using the DSP-TMS320F28335 Launchpad. With the reduced number of switching devices as well as the dc supply, the size of the inverter is compacted and becomes more economical.

Capacitor Voltage Balancing of a Grid-Tied, Cascaded Multilevel Converter with Binary Asymmetric Voltage Levels Using an Optimal One-Step-Ahead Switching-State Combination Approach

This paper presents a novel capacitor voltage balancing control approach for cascaded multilevel inverters with an arbitrary number of series-connected H-Bridge modules (floating capacitor modules) with asymmetric voltages, tiered by a factor of two (binary asymmetric). Using a nearest-level reference waveform, the balancing approach uses a one-step-ahead approach to find the optimal switching-state combination among all redundant switching-state combinations to balance the capacitor voltages as quickly as possible. Moreover, using a Lyapunov function candidate and considering LaSalle’s invariance principle, it is shown that an offline calculated trajectory of optimal switching-state combinations for each discrete output voltage level can be used to operate (asymptotically stable) the inverter without measuring any of the capacitor voltages, achieving a novel sensorless control as well. To verify the stability of the one-step-ahead balancing approach and its sensorless variant, a demonstrator inverter with 33 levels is operated in grid-tied mode. For the chosen 33-level converter, the NPC main-stage and the individual H-bridge modules are operated with an individual switching frequency of about 1 kHz and 2 kHz, respectively. The sensorless approach slightly reduced the dynamic system response and, furthermore, the current THD for the chosen operating point was increased from 3.28 to 4.58 in comparison with that of using the capacitor voltage feedback.