Spur Level Research Articles

An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit (FoMjitter) ~−236 dB.

Mathematical modelling and research of output spectrum of synthesizers based on high-speed DAC for 5G

The paper presents a mathematical model of the output signal of high-speed digital-to-analogue converters in special operating modes. This model simulates the output signal of a high-speed digital-to-analogue converters in time and frequency domain for the research of their frequency spectrum. The model consists of nonlinearities which cause undesirable frequency components (spurs) in the output spectrum. These are nonlinearities due to output signal sampling, phase code truncation and amplitude quantization errors. The paper describes PLL+DAC synthesizer which allows reducing the number and level of spurs in output spectrum.

A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications

In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than −88[Formula: see text]dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to −55[Formula: see text]dBc. Using the loop sampling technique provides a spur reduction of 33[Formula: see text]dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of −97/−99/−114[Formula: see text]dBc for 10[Formula: see text]kHz/100[Formula: see text]kHz/1[Formula: see text]MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6[Formula: see text]mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18[Formula: see text]mW.

An Ultra-Low-Power C-Band FMCW Transmitter Using a Fast Settling Fractional-N DPLL and Ring-Based Pulse Injection Locking Oscillator

Frequency-modulated continuous-wave (FMCW) signals-based radar systems can outrun the optical and ultrasound sensors in dark and severe weather conditions. FMCW radar systems require a fast settling frequency synthesizer to reduce the chirp signal’s inactive and modulation times. This work proposes a new C-B and FMCW Transmitter based on Fast Settling Fractional-N DPLL (FS-FNDPLL) and ring-based pulse injection locking oscillator (R-PILO). The proposed FS-FNDPLL generates an ultra-fast low-noise smooth narrowband chirp by introducing an automatic controller-based TDC switching (AC-TDCSw) scheme in the forward loop of FNDPLL. Also, the proposed FS-FNDPLL employs a new background gain calibrated digital-to-time converter (BGC-DTC) as a fractional divider in the feedback path for the quantization noise cancellation (QNC). The proposed FMCW transmitter uses an R-PILO to produce fast switching adjacent carriers after generating a narrowband chirp using FS-FNDPLL. The main features of the proposed FMCW to accelerate settling time with AC-TDCSw, BGC-DTC and the integration of spur suppressing pulse generator (SSPG) in R-PILO enable ultra-fast chirps with less phase noise and spur levels. The proposed transmitter up-converts the 500[Formula: see text]MHz narrowband chirp signal onto four adjacent carriers for obtaining a 2[Formula: see text]GHz chirp at the C-band. The simulation results prove that the proposed FMCW Transmitter consumes 79[Formula: see text]mW power. Furthermore, the phase noise of the proposed FS-FNDPLL is reduced to [Formula: see text][Formula: see text]dBc/Hz at 1[Formula: see text]MHz. The proposed FS-FNDPLL reduces the settling time to 1[Formula: see text][Formula: see text]s with the introduced AC-TDCSw scheme.

A Type-II Dual-Path PLL With Reference-Spur Suppression

To eliminate the unexpected spurs introduced by the charge pump (CP) mismatch in typical dual-path phase-locked loops (DP-PLLs), a fast calibration method incorporated in a prototype type-II PLL is presented. By enlarging the turn-on time and shrinking the charging capacitor, the CP mismatch can be amplified and detected more precisely in one reference period. Synchronously, a detection-quantization-compensation loop (DQCL) is built on the original DP-PLL, and it facilitates the procedure of mismatch calibration. By monitoring and compensating the equivalent mismatch voltage in a successive approximation (SA) pattern, the CP mismatch can be calibrated within five reference periods. Fabricated in 65-nm CMOS process, a 4.9–7-GHz DP-PLL is implemented. The measured output spur is suppressed by 9.11 dB at 5.46-GHz output after the calibration circuits are active. The measured output spur levels are less than −73 dBc throughout the whole output frequency range. The overall integral jitter (10 kHz–20 MHz) is less than 550 fs.

A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA

A wideband Internet of Things (IoT) transmitter (TX) employing open-loop binary frequency-shift keying (BFSK) modulator with a pseudo-randomized phase transition (PRPT) time and a single-supply Class-G harmonic rejection (HR) power amplifier (PA) is presented. The proposed open-loop phase switching modulator eliminates the data-rate limitation in a conventional phase-locked loop (PLL)-based closed-loop modulator, while the PRPT scheme increases the effective phase resolution with a better power efficiency than delta–sigma modulation (DSM)-based randomization. Thus, a low spur level below −40 dBc is achieved with only a 4-bit phase resolution. The Class-G HR PA, including a four-level supply voltage waveform generator, is proposed as a high-efficiency and low spurious PA architecture. The proposed HR PA presents the third- and fifth-harmonics cancellation over the 0.3-to-1-GHz band, while only a single supply is required for Class-G implementation of the HR PA. The proposed BFSK TX is implemented in a 55-nm CMOS process. Measured with a 0.3-to-1-GHz continuous-wave carrier, TX output power and PA drain efficiency are 2.7 ± 0.2 dB and 52% ± 3%, respectively, operating from a 0.9-V supply. The HRs of −31.4/−42.7 and −28.2/−42.4 dBc at the third/fifth harmonics are measured at the lowest (0.3 GHz) and the highest (1 GHz) carrier frequencies, respectively. With a data rate of 1 Mb/s, the measured FSK errors are 3.6% and 4.2% at both ends of the operating frequency.

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS

Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \!\Sigma $ </tex-math></inline-formula> loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks’ nonlinearities.

Low Phase Noise Direct-Modulation Optoelectronic Oscillator

A direct-modulation OEO (DM-OEO) generating stable 10 GHz and 20 GHz signals is presented. A single loop and a dual loop approach are implemented and compared. We show an output signal of 15 dBm RF power, and a phase noise as low as −135 dBc/Hz at 10 kHz offset from the 10 GHz carrier. The 20 GHz second harmonic exhibits a noise level of −127 dBc/Hz at 10 kHz. A high spur level reduction is also obtained in the dual loop architecture.

A 1.2 GHz jitter-peaking-free Integer-N PLL

In conventional charge-pump PLLs, if the third high-frequency pole is ignored, the system comprises of two poles and a zero. The transfer function of such a system is second-order low pass, which in some part of its frequency spectrum, the amplitude response |H| goes above unity. This translates to jitter-peaking, which in turn amplifies the input phase noise. Depending on damping factor or ζ, this jitter-peaking could be large or small. In this paper, a dual-path PLL with an additional Voltage Controlled Delay Line (VCDL) is presented that removes the jitter-peaking by adjusting the frequency values of the zero and poles in the PLL transfer function. In this new architecture, by increasing the VCO's gain (Kvco) the output phase noise is reduced. Designed and simulated in 65 nm CMOS and operating with a reference frequency of 12.5 MHz, the proposed PLL provides a spur level of −45dBc. The presented PLL exhibits an in-band phase noise of −117dBc/Hz at 1 MHz offset and total power consumption of 10.5 mW.

A Low Spur and Low Jitter Quadrature LO-Generator Using CML Inductive Peaking Technique for WLAN Transceiver

The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-mixing and DC offset issues, while spur levels are easily increased due to harmonic mixing, imbalance, and leakage of the SSB mixer. This article proposes a simple and innovative quadrature LO-generator, which adopts a current-mode-logic (CML) inductive peaking (IP) circuit to improve phase noise and suppress spurious tones. Four types of LO delivery methods using IP circuits are proposed and compared. Among four methods, the CML-IP circuit presents the optimum performance for driving long wires of multi-mm length. Instead of previous digital spur cancellation, the CML-IP circuit achieves higher spur suppression, lower jitter, and a greater figure of merit (FoM). The quadrature LO-generator can be configured to either VCO mode or bypass mode supporting external VCO input. Implemented in 55 nm CMOS technology, the proposed quadrature LO-generator achieves −52.6 dBc spur suppression, −142 dBc/Hz phase noise at 1 MHz offset at the 4.8 GHz frequency, and −271 FoM. Furthermore, the quadrature LO-generator occupies an active area of 0.178 mm2 and consumes 23.86 mW.

A 0.25–0.4-V, Sub-0.11-mW/GHz, 0.15–1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps

This article presents an ultra-low-voltage phase-locked loop (ULVPLL) with the minimum supply voltage at 0.25 V. The offset dual-path loop architecture is proposed to relax the charge pump (CP) current matching requirement. Thus, no current mismatch suppression technique is required. This significantly mitigates the CP design challenges at such low supply voltage. In the two proposed dynamic CPs (DCPs), all the current sources, current mirrors, and op amps in the prior CPs are eliminated. Hence, the CP voltage headroom requirement is relaxed to make the DCP be suitable for sub-0.3-V operation; meanwhile, the CP power consumption and circuit design complexity are simultaneously reduced. Implemented in 40-nm CMOS with core area of 0.00873 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the 0.15-1.6-GHz ULVPLL is capable of operation under a 0.25-0.4-V supply voltage. The power efficiency is 0.106 mW/GHz from 1.6-GHz output (at 0.4-V supply) and 0.048 mW/GHz from 0.2 GHz (at 0.25-V supply). Measured spur level is -58.3 dBc at 100-MHz offset from 1.6-GHz output (at 0.4-V supply) and -48.5 dBc at 12.5-MHz offset from 200-MHz output (at 0.25-V supply).

Towards an OFDM radar waveform for detection of far located targets with relatively low radar cross sections

The joint use of the OFDM waveform for radar as well as for communications has gained high attention recently. One problem that arises from using this waveform is the high spur level that appears on the range-velocity profile where it may eclipse an existing target of relatively small radar cross-section (RCS). This spur is due to nulling some subcarriers such as the DC-subcarrier. Another problem that results from using this waveform is the small maximum range which is far less than the unambiguous range. In our paper, we propose two diverse solutions to overcome the aforementioned problems. The first is based on using the Autoregressive (AR) model to address the problem of the high spur level. The second relies on repeating the same QAM modulated symbol through some subcarriers of the same OFDM symbol to address the problem of the relatively small maximum range. Our analysis and simulations show that applying our proposed methodology contributes to efficiently reducing the spur level from one side, and extending the maximum range to the limit of the unambiguous range from the other side. Furthermore, a trade-off is offered between the data rate of the communication system and the maximum range of the radar.

Optoelectronic reference X-band oscillator for radar systems

We present the design and results of studying the characteristics of an optoelectronic microwave oscillator in the free-running regime are presented, propose a method for synchronising it with a signal of a highly stable crystal oscillator using a phase-locked loop, and analyse the results of an experimental study on the frequency instability of an optoelectronic microwave reference oscillator. The optoelectronic microwave reference oscillator with optical gain and a 10 GHz oscillation frequency simultaneously provides ultra-low phase noise (less than – 142 dB Hz−1) at a 10 kHz frequency offset from the microwave carrier and a low level of spurs in the oscillation spectrum (no more than – 94 dBc). In this case, the temperature coefficient of the oscillation frequency is determined by the temperature instability of a highly stable crystal oscillator.

A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain

This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), which relies on gate delay in the time domain, power-efficient quantization of PE by the proposed conversion scheme in the FDV domain can be accomplished with a higher power-supply/common-mode rejection ratio (PSRR/CMRR), lower process, voltage, and temperature (PVT) sensitivity, finer resolution, and better linearity. The implemented DPLL covers the fractional-N operation by a 10-bit differential current digital-to-analog converter (DAC) with a resistive load to represent the fractional phase/time. A differential dv/dt ramp is employed to linearly transfer the preset initial voltage into a small phase/voltage error, which is digitized by a narrow-range fine-resolution 7-bit self-timed successive-approximation-register analog-to-digital converter (SAR-ADC). The prototype DPLL, implemented in 130-nm CMOS, achieves 101-fs rms jitter, integrated from 10 kHz to 40 MHz, in the fractional-N mode with sub-12-bit fractional-frequency-control words, using an 80-MHz reference clock (REF), consuming 9.2 mW. This corresponds to a figure of merit (FoM) of -250.3 dB. The measured worst case fractional spur level is -56 dBc.

A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation

In this article, a fractional- $N$ reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor-based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be effectively suppressed with the high-gain setting for the RSPD when the loop is in lock. The linear range of RSPD can be programmed to cover the quantization error in a frac- $N$ mode without degrading the PLL in-band phase noise. To mitigate the nonlinearity of RSPD, the CDAC is implemented with a high-order cancellation scheme using only one capacitor array but multiple reference voltages. The prototype chip was fabricated in a 45-nm partially depleted silicon-on-insulator (PDSOI) CMOS process. The measurement showed an output frequency range covering 7.7–9.1 GHz with an integrated jitter (10 kHz–50 MHz) of 135 fs and an in-band fractional spur level of −55 dBc at an offset frequency of 50 kHz. The entire PLL consumes 4.5 mW and achieves an figure of merit (FoM) of −250.8 dB.

A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth

A 4-GHz sub-harmonically injection-locked phase-locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve low phase noise. The phase noise of the proposed ILPLL was −112.3 dBc/Hz at 1-MHz offset frequency, whereas that of the conventional PLL was −104.8 dBc/Hz. The measured integrated jitter from 10 kHz to 30 MHz was 710 fs, and the corresponding reference spur level was −61.6 dBc with the proposed calibration technique. Fabricated in a 28-nm CMOS process, the proposed ILPLL occupies 0.09 mm2. Operating at 4 GHz, it consumes 11.4 mW from a 1.0-V power supply.

Low spur frequency synthesiser using randomly shifted reference spur to higher frequencies

ABSTRACT A low spur frequency synthesiser is proposed based on the frequency-hopping spread spectrum which is employed on the control voltage of the voltage-controlled oscillator. A spur reduction circuit is inserted between the phase-frequency detector and charge pump to randomly shift the spur to higher frequencies to suppress the reference spur. In order to achieve this, the proposed technique uses the time to voltage converter and the voltage to time converter and a linear feedback shift register. Through shifting and randomising the periodic ripples on the control voltage to high frequencies, the amplitude of the reference spur is attenuated. The proposed structure eliminates the need for decreasing bandwidth and reducing the VCO gain to suppress the reference spur. A 2.08–2.22 GHz frequency synthesiser is designed and a post-layout simulation is performed using the 180 nm CMOS technology. The reference spur level of −91.25 dBc is achieved. The presented structure provides an additional spur reduction of 32.88 dB compared to a conventional frequency synthesiser and also provides the best-normalised reference spur rejection in the literature. Settling time is obtained when the output frequency is switched from 2.1 to 2.08 GHz.

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency. Unlike the typical type-II single-loop PLL using a tri-state phase-frequency detector (PFD) plus a charge pump (CP) that has several limits in high-speed operation, our proposed PLL features a dual-loop scheme to enhance its performance and operating speed at low power. Specifically, we propose a dynamic frequency detector (FD) and a phase detector (PD) in conjunction with voltage-to-current converters (VICs) to avoid the typical current-mode-logic (CML) circuitry for static power reduction. Prototyped in 65-nm CMOS process, the entire PLL dissipates 10.6 mW, of which the dynamic FD and PD merely consume 0.28 mW. The integrated jitter is 415.6 fs rms (10 kHz to 100 MHz) and the reference spur level is -53 dBc at a 26.4-GHz output.

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

This brief presents an injection-locked PLL (ILPLL) that offers better jitter performance for high-speed clock generation. By analyzing and adjusting a phase domain response (PDR) of the injection-locked oscillator (ILO), the injection strength at the target frequency of 15 GHz is maximized with the lowest deterministic noise. In addition, a pulse generator that limits the maximum operating speed in the conventional ILPLL is removed to achieve the highest synthesizable clock frequency. Fabricated in 28-nm CMOS technology, the proposed ILPLL occupies an active area of 0.03 mm2 and dissipates 17.8 mW at 15 GHz with a 1.3-V supply voltage. The measured integrated jitter from 1 kHz to 40 MHz at the point of maximum injection strength is 213 fs and the corresponding reference spur level is −43 dBc.

A 39-GHz Frequency Tripler With &gt;40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS

The generation of the carrier signal with a very low spur level is a key challenge in all the communication systems, especially those operating at mm-waves, where a frequency multiplier is typically used to break the tradeoff between high frequency of operation and low phase noise. This letter describes a frequency tripler tailored to cover the fifth generation new radio 39-GHz frequency range. By embracing the edge-combining concept, together with the combination of a single-stage polyphase filter and a multipoint injection-locked ring oscillator, the proposed frequency multiplier is able to offer robust and consistent high harmonic rejection ratio over a large fractional bandwidth. Fabricated in 28-nm bulk CMOS technology, the measured frequency multiplier features >40-dBc harmonic rejection over an outstanding 35% fractional bandwidth, while consuming 25 mW only from 0.9-V supply. To the best of our knowledge, the proposed multiplier achieves the highest harmonic rejection among the state-of-the-art multipliers in CMOS and BiCMOS technologies, while having 60% smaller area.