In spite of advances to improve cache efficiency, memory access bottlenecks still prevent processors from executing at full speed. This paper introduces the concept of using a secondary bus, connecting the level-2 cache to memory, for retiring cache write-backs. Simulations, using the sim-alpha version of the SimpleScalar tool set, demonstrate the feasibility and possible advantages of such a secondary bus. Based on simulation results, the added secondary bus can decrease queuing delays on the system bus by 75–90% when sufficient write-backs are present. Such reduction in queuing delays offers superior temporal determinacy in real-time environments. Real-time and near real-time embedded applications that depend on intense graphics processing and movement of large blocks of data, such as printer controllers and medical imaging, are prime candidates for applications of the secondary bus. The feasibility of implementing such a secondary bus using a serial line or wireless technology is also discussed.