Level Converter Research Articles

Design of Voltage Level Shifter Using CNTFETs

Level shifters (LSs) are used to interface with different voltage domains. In this work, a voltage LS is presented for different ranges of input–output voltage conversion. This design presents a high-speed, energy-efficient and robust dual-supply level converter based on multi-threshold carbon nanotube FETs (CNTFETs). The chirality of CNTs is suitably chosen to adjust the threshold voltage of CNTFETs. The proposed circuit is capable of shifting the input voltage level from the deep sub-threshold (0.25 V) to the above-threshold domain (0.45 V) and above-threshold (0.45 V) to nominal voltage domain (0.9 V). The results of the simulation are obtained based on the MOSFET-like CNTFET model at 32 nm technology node. The proposed circuit exhibits an average propagation delay of $$\sim$$ 63 ps and $$\sim$$ 32 ps, for two different voltage levels, respectively, and dissipates lesser static power than the existing circuits based on CNTFET.

Assessment Indexes for Converter P-Q Control Coupling

This work presents a concise methodology for the calculation of assessment indexes regarding the coupling between active and reactive power control observed on distribution level converters. First, the reader is introduced to the concept of power coupling; when, where and how it appears in power control of converters. A brief summary of the theory and formulation behind it is also included, together with relevant literature. Then, the methodology for the assessment of active and reactive power control performance of any grid-connected converter is presented. The impact of small control disturbances during a testing procedure is monitored, analyzed and converted to meaningful indexes, so that the type and level of coupling is quantified without putting the converter or the grid at risk. The efficiency of the methodology to assess the type and level of coupling is verified experimentally. This is done by assessing several power control approaches with different level of decoupling efficiency on the same power converter connected to a distribution grid. While the assessment is performed with safe, minimal disturbances, its exceptional accuracy is later confirmed by the level and type of coupling observed during significant power step changes.

Performance comparison of series and parallel damped LCL filters using 5-level voltage source converter

The high harmonic content produced by conventional converters has resulted in the increased system size and cost, due to the need for large-sized low-order harmonic passive filters and cooling system requirement. Given that, multilevel inverters and special modulation techniques were developed to suppress or eliminate the low-frequency harmonics and the left behind high-order ones are eliminated using a high-frequency small-sized filter. Hence, this paper designs and compares the total harmonic distortion (THD) and efficiency values of three set of filters, namely LCL filter, LCL with series and parallel resistance on a novel five-level multilevel voltage source inverter topology. The novelty lies with the proposed inverter, which, apart from using a single direct current source, it can extend it elimination capability beyond the normal five level using the concept of multiple switching per step and an optimised selective harmonic elimination pulse width modulation. The converter can eliminate eleven lower-order odd nontriplen harmonics, hence making the 37th harmonic at 1.85 kHz to be the first dominant harmonic. At 2-kW loading, two of the filters have THD below 5%, therefore satisfying the IEEE 519 standard. The parallel resistance damped filter (LCL-P-R) has less THD value but poor efficiency due to the resistance introduced into the circuit. The study was carried out using PSIM and MATLAB software.

Practical Considerations for Designing Reliable DC/DC Converters, Applied to a BIPV Case

State-of-the-art reliability assessment typically starts from a given circuit topology, for which the most suitable components are selected using a Physics of Failure analysis. This paper, however, addresses the topology selection stage, which is the foundation in designing reliable converters. Based on an overview of the reliability performance of different components, a methodology is presented as a guideline for comparing topologies to one another. The focus is directed at practical consequences associated with certain designs. Furthermore, an overview is provided on the latest developments in component technology reliability improvements. The developed methodology is mainly intended for demanding applications, where long lifetimes are required or elevated ambient temperatures are present. After the topology selection, an overview of possibilities is given that allows further increasing converter availability. Finally, the methodology is applied to the design of module level converters for building integrated photovoltaics, which is a high temperature application with a high desired lifetime. A prototype and experimental results are presented.

Control of Modular Multilevel Converter Fed 3-Phase Induction Motor using DTC with PI Controller

In this paper 3-level Modular Multilevel Converter fed direct torque control (DTC) of Induction Motor (IM) is proposed. The proposed Modular Multilevel Converter (MMC) replaces a three-level Neutral Point Clamping (NPC) converter to drive an Induction Motor, because of its high voltage power range. The main drawback of the DTC of NPC fed IM using conventional PI controller is high torque, stator flux ripples and speed of IM is decreasing under transient and steady state operating conditions. The work of this paper is to study, evaluate and compare the techniques of the conventional DTC with NPC and DTC with MMC using PI controller, applied to the induction motor through MATLAB/Simulation.

Modelling and simulation of dual sourced front-end converter for hybrid electric vehicles

The paper is concerned with Modelling and simulation of dual sourced front end converter for Hybrid electric vehicles (HEV). In this research work with the help of the renewable multilevel integrated SRM drive converter, different operating conditions are obtained by changing the ON-OFF positions of the front-end switches and the performance of HEV is observed based on the power interface between the battery and the fuel cell. To provide the phase voltage, a battery bank is used for fast demagnetisation and excitation in fuel cell driving mode. The function of 4-level converter is to generate multi-level output voltages while the battery acts as a source. An additional capacitor is introduced to enhance the torque capacity of a capacitor. During driving mode, the proposed converter integrates battery and fuel cells with a smaller number of power switches and without energy storage devices. Due to its flexible energy conversion, the proposed converter is easy to manufacture and replace owing to its modularised structure. The converter speed and efficiency remain the same even when the converter is integrated with the battery and fuel cell. Simulation on a three-phase SRM confirms the effectiveness of the proposed converter.

A Half Adder Design Based on Ternary Multiplexers in Carbon Nano-Tube Field Effect Transistor (CNFET) Technology

In this paper a ternary half adder is proposed and designed using carbon nano-tube field effect (CNFET) transistors. This novel design in ternary logic is based on multiplexers and level converters. The performance of the proposed design is examined against different supply voltages and a range of temperatures and fan-outs. Propagation delay time, power consumption, power-delay product (PDP) and transistor count are compared between the proposed ternary half adder and prior works. It is shown that the delay time in the proposed design can be improved by 75% with respect to other works while the PDP can be improved at least by 5%. Moreover, the transistor count in the novel design is less than other works at least by 10%. Therefore, it can be a promising candidate for the design of next generation of adder circuits in digital logic systems and ALU blocks.

A 0.3-V to 1.8–3.3-V Leakage-Biased Synchronous Level Converter for ULP SoCs

This letter proposes a robust synchronous wide-range clocked level converter (LC) that converts subthreshold input signals to high I/O voltages for ultra-low power (ULP) SoCs. By biasing the circuit using nMOS leakage current, the design offers robust operation across a wide range of low- and high-supply voltages as well as PVT variations. The design was fabricated in 55-nm CMOS process and shows 60.5-fJ ( $V_{\mathrm{ DDH}}=2.5$ V) switching energy, marking a $2.6\times $ improvement over prior works.

A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3–1.2-V Range or 44-fW Leakage at 0.8–2.5-V Range

This letter presents an ultralow-leakage level converter design based on dynamic leakage-suppression (DLS) logic for battery-less Internet-of-Things systems. The design is compact and simple, consisting of six transistors arranged as two digital buffers in series and requires only a single voltage supply corresponding to the high-voltage domain. We analyze the dc switching characteristic of the proposed level converter to create a design guideline which we use to implement two designs that target core (0.3-V to 1.2-V conversion) and I/O (0.8-V to 2.5-V conversion) voltage domains. We fabricated the designs in 65-nm CMOS and present measurements from 17 dies. The core design achieves 8.18 fJ per transition with 2.56 pW of leakage power, while the I/O design achieves 54.23 fJ per transition and 44 fW of leakage power.

A Simplified Virtual Vector PWM Algorithm to Balance the Capacitor Voltages of Four-Level Diode-Clamped Converter

The voltage balancing problem of dc-link capacitors in multilevel diode-clamped converters limits their applications in industry under some operational conditions. Virtual vector PWM (VVPWM) can attain the capacitor voltage balancing under all operational conditions but it increases the complexity and computation burden by increasing the number of triangular regions for higher levels as compared to conventional space vector PWM (CSVPWM). In order to solve the dc-link voltage balancing problem in four-level diode-clamped converter, a simplified virtual vector PWM (SVVPWM) algorithm is proposed in this paper. The pair of new virtual vectors is defined in such a way that the space vector diagram of four level converter is transformed into three level space vector diagram that lessens the complexity and computation burden by decreasing the number of triangular regions. The balancing of capacitor voltages can be achieved by using proposed SVVPWM algorithm for the whole range of modulation index load power factor. Steady state and dynamic performance of the SVVPWM algorithm is verified through the simulations and experiments.

Evaluation of high power density achievement of optimum 4‐level capacitor‐clamped DC–DC boost converter with passive lossless snubber circuit by using Pareto‐Front method

This study presents the evaluation of the proposed optimum 4-level capacitor-clamped DC-DC boost converter (CCBC) for high power density achievement by using Pareto-Front method. The 4-level CCBC with considering high switching frequency can greatly reduce the inductor size and volume. High switching frequency caused the switching devices to suffer high semiconductor losses. Consequently, the cooling device volume is increased as well. Thus, this study presents soft-switching technique in the 4-level CCBC for semiconductor losses reduction. The combination of optimum design of inductor, improvement of circuit structure and soft-switching technique may lead to the highest power density of the converter. A 400 W of the 4-level CCBC converter is designed and experimentally verified. The results show that the inductance and inductor volume required in the 4-level CCBC is reduced by 88.89 and 80.75%, respectively. Besides, Pareto-Front curve shows the highest power density of soft-switching technique with the proposed 4-level CCBC is 6.51 kW/dm 3 at 800 kHz of switching frequency with efficiency of 97.20%.

A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.

Design of a Single Phase H- Bridge Cascaded Multi Level Inverter (9 Level) for Solar Powered Utilities

Nine level inverter and converter which is used for solar powered utilities was proposed. The inverter has 7 switches in main circuit and 1 switch for high frequency switching for the generation of nine level output. The output in the inverter reduces overall THD, loss due to switching and improves the efficiency of the power in the output. In this paper the control circuit is simplified by using capacitors to balance the voltage automatically. Using MATLAB/Simulink simulation results are explained in detail.

Capacitor Voltage Balancing and Stabilization for 4-Level Hybrid-Clamped Converter Using Selected Switching States

Without active control, the voltage fluctuations of the dc-link and flying capacitors in a 4-level hybrid-clamped converter (4L-HCC) become excessively large in low-frequency operation. This paper studies the switching state redundancy inherent in a 4L-HCC and proposes a new capacitor voltage balancing and stabilizing method to minimize the dc-link and flying capacitor voltage fluctuations. A straightforward algorithm is developed based on a logic table to select the suitable switching states. Verified by simulation and experimental testing results, the new method and algorithm virtually eliminate all the big voltage fluctuations of capacitors at low and zero frequencies, greatly enhancing the robustness and reliability of a 4L-HCC. The capacitor size can be reduced by more than 80% compared with the conventional method.

Detection and Mitigation of faults in Cascaded H-bridge 13 - Level Converter STATCOM

This paper deals with the detection and mitigation of faults in 13-level converter STATCOM. The FACTS device used is flexible in reactive power compensation, voltage regulation, to reduce harmonics of the grid that must be protected from faults in the switches. Due to frequency switching of the STATCOM, the possibility of the switch malfunction such as open circuit and short circuit faults are predominant. Many static synchronous compensators use multilevel converters to lower the switching faults. The pulse width modulation techniques applied to a proposed cascaded 13-level to detect the faulty switch and mitigate it.In this paper the performance analysis of PWM techniques are computed with dynamic fault conditions.

NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power Design

Power dissipation has become a major concern in nanoscale integrated circuits. The power gating and dual-supply design methods are among the most effective approaches for reducing the static and dynamic power consumptions. However, these methods require efficient data retention and voltage level conversion. In this paper, a nonvolatile level converter flip-flop (NVLCFF) is proposed to be used in ultra-low-power integrated circuits. Our proposed NVLCFF employs the magnetic tunnel junction (MTJ) for data retention. Spin transfer torque along with the spin Hall effect is used for reconfiguring the MTJs. The peripheral circuitry is designed using 7-nm FinFET as one of the leading industrial technologies. Furthermore, to facilitate the use of the dual-supply approach, voltage level conversion is performed in the structure of the proposed NVLCFF. According to the HSPICE simulations, the power consumption, backup energy and restore energy of the proposed circuit are on average 59%, 48% and 92% lower than the other NVLCFFs based on the previous nonvolatile flip-flops with different MTJ structures. Furthermore, the comprehensive Monte Carlo simulations indicate the robustness of the proposed design in the presence of major MTJ and FinFET process variations as compared to the previous designs.

Integrated fuzzy and phase shift controller for output step voltage control in multilevel inverter with reduced switch count

ABSTRACTA modified multilevel inverter with a configurable level generation is proposed in this paper. The MLI is composed of a modified boost converter at the front end followed by a level generation circuit and a H-bridge configuration. The front-end converter is biased with a PV source with a Hybrid boost resonant converter. The switches are triggered out of phase through a MPP tracker which uses Fractional INC MPPT. The secondary side of the circuit is composed of a derived voltage doubler along with the voltage regulator. The output of the doubler is regulated through a level converter which integrates a fuzzy controller and a phase shift controller. The modified multilevel inverter uses a low-voltage PV source as input and generates a variable-step multilevel output voltage with lower harmonic distortion and it is suitable for low-power PV applications.

A Hybrid 7-Level Inverter Using Low-Voltage Devices and Operation With Single DC-Link

This paper proposes a new 7-level inverter topology for induction motor drives. It is a hybrid topology formed by cascading a 5-level active neutral-point-clamped inverter with a 3-level T-type converter. It is obtained using low-voltage semiconductor devices with voltage blocking capability of Vdc/3 and Vdc/6. The topology uses three floating capacitors per phase, which are balanced within a pulsewidth modulation (PWM) switching duration using switching-state redundancies for each pole-voltage level. Topology forms two stacks at the front-end, which requires individual symmetrical dc source. The analysis of switching loss and conduction loss is performed and compared with some of the existing 7-level multi-level inverters reported in various literatures to show the advantages of the proposed topology. Furthermore, the single dc source operation with two stacked capacitors and closed-loop control of neutral-point voltage using symmetrical six-phase induction motor is proposed. The voltage-control algorithms for floating capacitors and dc-link stacked capacitors are proposed, which are independent of load power factor and modulation index. Open-loop V / f and closed-loop rotor field oriented control are performed, and various results at steady and transient states are presented to validate the aforementioned claims.

Research on electrified railway power router based on 81 level conversion technology

On the premise of realizing the application of renewable energy power generation in traction power supply system, aimed at the problems of power scheduling and operation cost in the traction network of 27.5 kV electrified railway, a kind of electrified railway energy router device based on 81 level conversion technology is proposed. The device adopts 81 level converter to realize the high voltage, high power quality and high power demand of grid-connected converter for electrified railway energy supply system. The energy dispatching mode of voltage-phase angle is adopted to ensure the normal power supply of electric locomotive and the voltage support of traction network. At last, the bidirectional converter of the energy storage unit realizes peak cutting and valley filling of energy and ensures the stability of renewable energy generation. Based on the theoretical study of the topology, technical principle, energy scheduling calculation and control strategy of the new electrified railway power router, the device was simulated and verified, and the effectiveness of the electrified railway power router technical solution was verified.

A high voltage direct current transmission system : natural and selective harmonic cancellation

<p class="AbsKeyBibli"><span lang="EN-US">This study focused on the special High Voltage Direct Current technology. The context is given by combining two original solutions; the first solution, using a natural harmonic cancellation, consists to connect in series two classical frequency inverters which are coupled to the grid through a specific transformer connection. On the other hand, the second solution is achieved by using three, five or more level converters in square wave modulation, in order to eliminate some selective harmonics by optimizing a switching angle. The simulation and experimental results indicate that the proposed High Voltage Direct Current transmission systems offer high efficiency, unity power factor and better current and voltage quality with fewer harmonic.</span></p>