Length Of Input Data Research Articles

Predicting Slurry Pressure Balance with a Long Short-Term Memory Recurrent Neural Network in Difficult Ground Condition.

The safety of tunneling with shield tunnel boring machines largely depends on the tunnel face pressure, which is currently decided by human operators empirically. Face pressure control is vulnerable to human misjudgment and human errors can cause severe consequences, especially in difficult ground conditions. From a practical perspective, it is therefore beneficial to have a model capable of predicting the tunnel face pressure given operation and the changing geology. In this paper, we propose such a model based on deep learning. More specifically, a long short-term memory (LSTM) recurrent neural network is employed for tunnel face pressure prediction. To correlate with PLC data, linear interpolation is employed to transform the borehole geological data into sequential geological data according to the shield machine position. The slurry pressure in the excavation chamber (SPE) is taken as the output in the case study of Nanning Metro, which is confronted with the clogging problem due to the mixed ground of mudstone and round gravel. The LSTM-based SPE prediction model achieved an overall MAPE and RMSE of 3.83% and 10.3 kPa, respectively, in mudstone rich ground conditions. Factors that influence the model, including different kinds and length of input data and comparison with the traditional machine learning-based model, are also discussed.

Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

In this paper, we propose a low-power memory-based computing architecture, called selective computing architecture (SCA). It consists of multipliers and an LUT (Look-Up Table)-based component, that is multi-context ternary content-addressable memory (MC-TCAM). Either of them is selected by input-data conditions in neural-networks (NNs). Compared with quantized NNs, a higher accurate multiplication can be performed with low-power consumption in the proposed architecture. If input data stored in the MC-TCAM appears, the corresponding multiplication results for multiple weights are obtained. The MC-TCAM stores only shorter length of input data, resulting in achieving a low-power computing. The performance of the SCA is determined by three physical parameters concerning the configuration of MC-TCAM. The power dissipation of the target NN can be minimized by exploring these parameters in the design space. The hardware based on the proposed architecture is evaluated using TSMC 65 nm CMOS technology and MTJ model. In the case of speech command recognition, the power consumption at the multiplication of the first convolutional layer in a convolutional NN is reduced by 67% compared to the solution relying only on multipliers.

Increasing the input data length of RSA cryptosystem by applying a hybrid lossless data compression algorithm

RSA is a well-known and widely used cryptosystem. One major limitation of RSA is its maximum input length depends on the chosen key size and the selected padding. This paper proposed a hybrid data compression algorithm to increase the input data length to be encrypted by RSA. Firstly, a plain text is compressed by the LZW algorithm. The compressed data is padded. After that, the size of the compressed data is further reduced by using continued fraction. Double-compressed data is, then, used as an input of RSA. When using a combination of continued fraction and LZW algorithm, the results showed that, on average, the input data length is increased by 18.91 per cent. In most cases, the processing time is much better than not doing any compression. In the case of decryption, a cipher text is decrypted by RSA first. The padding is removed. Then, the Euclidean algorithm and LZW are used respectively to restore the original data. The hybrid data compression is not only relieved the limitation of RSA but also enhances the security level.

Design and implementation of single bit error correction linear block code system based on FPGA

Linear block code (LBC) is an error detection and correction code that is widely used in communication systems. In this paper a special type of LBC called Hamming code was implemented and debugged using FPGA kit with integrated software environments ISE for simulation and tests the results of the hardware system. The implemented system has the ability to correct single bit error and detect two bits error. The data segments length was considered to give high reliability to the system and make an aggregation between the speed of processing and the hardware ability to be implemented. An adaptive length of input data has been consider, up to 248 bits of information can be handled using Spartan 3E500 with 43% as a maximum slices utilization. Input/output data buses in FPGA have been customized to meet the requirements where 34% of input/output resources have been used as maximum ratio. The overall hardware design can be considerable to give an optimum hardware size for the suitable information rate.

NEURAL NETWORKS FOR SHAPE RECOGNITION BY MEDIAL REPRESENTATION

Abstract. The article is dedicated to the development of neural networks that process data of a special kind – a medial representation of the shape, which is considered as a special case of an undirected graph. Methods for solving problems that complicate the processing of data of this type by traditional neural networks – different length of input data, heterogeneity of its structure, unordered constituent elements – are proposed. Skeletal counterparts of standard operations used in convolutional neural networks are formulated. Experiments on character recognition for various fonts, on classification of handwritten digits and data compression using the autoencoder-style architecture are carried out.

Efficient PSoC Implementation of Modular Multiplication and Exponentiation Based on Serial-Parallel Combination

This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated as Programmable System on Chip (PSoC) where the processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between time execution, occupied area and flexibility. The implementation of these operations on such environment requires taking into account several criteria. Indeed, the Hardware (HW) architectures data bus should be smaller than the input data length. The design must be scalable to support different security levels. The implementation achieves optimums execution time and HW resources number. In order to satisfy these constraints, Montgomery Power Ladder (MPL) and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution times. The application for 1024-bits data length shows that the MMM run in 6.24[Formula: see text][Formula: see text]s and requires 647 slices. The ME is executed in 6.75[Formula: see text]ms using 2881 slices.

REAL TIME RIVER-STAGE PREDICTION BY ANN WITH OBSERVED RAINFALL AND RIVER-STAGE INFORMATION

This research is a development of our previous work, which was also based on artificial neural network usage for prediction of water levels at Hirakata station. This time we included rainfall information along with upstream water level data. The developed model uses a single hidden-layered feed-forward neural network. Prediction accuracy increased significantly compared to the previous research using a similar model. Regarding the whole validation period of three years, even though the model followed a certain pattern of decreasing performance with increasing lead time and increasing length of input data, the results still outperformed predictions obtained without using rainfall information. Some particular periods with peak events from the validation period were also checked. While all the results exhibited better outcomes compared to the previous model, this model did not follow a specific pattern corresponding with input data selection in any of these check periods.

Realization of Second-Order Structure of Recursive Algorithm for Discrete Cosine Transform

A computational and hardware-efficient second-order infinite impulse response filter structure is proposed in this paper. It can compute discrete cosine transform (DCT) with improved processing speed and is valid for N = 2r, where N is the length of the input sequence and r > 1. A new algorithm is also proposed in this paper which is an improvement over previously reported algorithms in the literature. The proposed algorithm reduces the total number of real multiplications and additions in comparison with the existing algorithms. Using the suggested algorithm, computational cycles required to compute a DCT coefficient are less which further reduces the truncation error while processing a long length of input data.

Electroencephalography‐based feature extraction using complex network for automated epileptic seizure detection

AbstractElectroencephalography signals are typically used for analyzing epileptic seizures. These signals are highly nonlinear and nonstationary, and some specific patterns exist for certain disease types that are hard to develop an automatic epileptic seizure detection system. This paper discussed statistical mechanics of complex networks, which inherit the characteristic properties of electroencephalography signals, for feature extraction via a horizontal visibility algorithm in order to reduce processing time and complexity. The algorithm transforms a time series signal into a complex network, which some features are abbreviated. The statistical mechanics are calculated to capture distinctions pertaining to certain diseases to form a feature vector. The feature vector is classified by multiclass classification via a k‐nearest neighbor classifier, a multilayer perceptron neural network, and a support vector machine with a 10‐fold cross‐validation criterion. In performance evaluation of proposed method with healthy, seizure‐free interval, and seizure signals, firstly, input data length is regarded among some practical signal samples by optimizing between accuracy‐processing time, and the proposed method yields outstanding performance on the average classification accuracy for 3‐class problems mainly for detection of seizure‐free interval and seizure signals and acceptable results for 2‐class and 5‐class problems comparing with conventional methods. The proposed method is another tool that can be used for classifying signal patterns, as an alternative to time/frequency analyses.

A detailed experimental study of a DNA computer with two endonucleases.

Great advances in biotechnology have allowed the construction of a computer from DNA. One of the proposed solutions is a biomolecular finite automaton, a simple two-state DNA computer without memory, which was presented by Ehud Shapiro's group at the Weizmann Institute of Science. The main problem with this computer, in which biomolecules carry out logical operations, is its complexity - increasing the number of states of biomolecular automata. In this study, we constructed (in laboratory conditions) a six-state DNA computer that uses two endonucleases (e.g. AcuI and BbvI) and a ligase. We have presented a detailed experimental verification of its feasibility. We described the effect of the number of states, the length of input data, and the nondeterminism on the computing process. We also tested different automata (with three, four, and six states) running on various accepted input words of different lengths such as ab, aab, aaab, ababa, and of an unaccepted word ba. Moreover, this article presents the reaction optimization and the methods of eliminating certain biochemical problems occurring in the implementation of a biomolecular DNA automaton based on two endonucleases.

TCP-Gvegas with prediction and adaptation in multi-hop ad hoc networks

TCP Vegas performance can be improved since its rate-based congestion control mechanism could proactively avoid possible congestion and packet losses in multi-hop ad hoc networks. Nevertheless, Vegas cannot make full advantage of available bandwidth to transmit packets since incorrect bandwidth estimates may occur due to frequent topology changes caused by node mobility. This paper proposes an improved TCP Vegas based on the grey prediction theory, named TCP-Gvegas, for multi-hop ad hoc networks, which has the capability of prediction and self-adaption, as well as three enhanced aspects in the phase of congestion avoidance. The lower layers' parameters are considered in the throughput model to improve the accuracy of theoretical throughput. The prediction of future throughput based on grey prediction is used to promote the online control. The optimal exploration method based on Q-Learning and Round Trip Time quantizer are applied to search for the more reasonable changing size of congestion window. Besides, the convergence analysis of grey prediction by using the Lyapunov's second method proves that a shorter input data length of prediction implies a faster convergence rate. The simulation results show that the TCP-Gvegas achieves a substantially higher throughput and lower delay than Vegas in multi-hop ad hoc networks.

A CONCURRENT ERROR DETECTION SCHEME FOR TOTALLY SELF CHECKING FPGA LOOK-UP TABLE

Field Programmable Gate Arrays are widely useful in mission critical applications. FPGAs have fixed architecture; it has the capability to change function in situ for a particular application. SRAM based FPGAs are vulnerable to Single Event Upsets (SEUs), which poses unintended change to the logic functions on exposure. The project proposed is a unidirectional error detection scheme i.e., Scalable Error Detection Coding (SEDC) scheme, for use in FPGA Look-up tables. The SEDC check bits are generated along with the programming bits and it is stored on the FPGA SRAM cells during the normal operation of the LUTs. The programming bits are processed to check bit generator where corresponding code bits are generated for the programming bits. The newly generated code bits are compared with the pre-stored code bits. Any single or multiple unidirectional errors as a result of SEU is detected by this scheme. Scalability is the significant advantage of this scheme it can be scaled to any input data length. With the increase in input data length, only the area gets scaled while the latency remains constant irrespective of the binary data length. The implemented algorithm achieves 100% error detection. The Proposed SEDC scheme is simulated using Tanner EDA tool and the layouts are generated using Microwind.

개인정보암호화에 효율적인 새로운 형태보존암호화 알고리즘

ABSTRACT Recently financial institutions and large retailers have a large amount of personal information leakage accident occurred one after another, and the damage is a trend of increasing day by d ay. Regulation such as enforcing the encryption of the personal identification information are strengthened. Efficient technolo gy to encrypt personal information is Format-preserving encrypt ion. Typical encryption expand output data length than input data le ngth and change a format. Format Preserving Encryption is an efficient method to minimize database and application modificat ion, because it makes preserve length and format of input data. In this paper, to encrypt personal information efficiently, we propose newly Format Preserving Encryption using Block cipher mode of operation. Keywords: Format-Preserving Encryption; Modes of Operation; Block cipher ; Data format; Data Length I.서 론 국내외를 불문하고 대량의 개인정보유출사고가 연이어 발생하고 있고, 이에 따라 개인정보보호법 개정 접수일(2014년 6월 17일), 수정일(2014년 8월 5일), 게재확정일(2014년 8월 5일)†주저자, km8944@korea.ac.kr‡교신저자, jcsung@uos.ac.kr(Corresponding author)

Design and Implementation of an FFT Phase Difference Measuring Method

The conventional phase difference measuring methods in the phase shift laser range finder are usually implemented with complex hardware circuits and phase discrimination algorithm. In this paper an FFT phase difference measuring method is designed and implemented based on STM32F407VG microcontroller. This method takes the advantage of the pre-set and fixed frequency of the beat signal by setting the analog-to-digital conversion rate precisely and making the input data length of FFT integral multiples of the beat signal period. In this way spectrum correction is no need. The hardware circuits and phase discrimination algorithm is simplified. The test results show that the phase difference measuring accuracy of 1/12000 is achieved.

震源過程と津波観測波形を用いたハイブリッド型リアルタイム津波予測法

Although a real-time tsunami prediction method which uses observed tsunami waveform as input data for an inversion analysis is effective for non-structural measures, the method needs to wait several-ten-minutes for observed data acquirement. To solve this disadvantage, authors propose the hybrid method which uses not only observed tsunami waveforms but also source rupture process estimated from strong motion seismogram. Unit tsunami source grids for inputs of inversion analysis are selected considering source rupture information. Restraint condition between neighbor unit source grids is employed to estimate the initial tsunami displacement smooth. Effectiveness of additional observation points are discussed to improve the accuracy and reduce the length of input data. The appropriate combination of source rupture process, restraint condition, and additional observation points are effective to improve the accuracy of the real-time tsunami prediction in Tohoku coasts.

효율적인 블록 인터리버 파라미터 블라인드 추정 기법

최근 블라인드 신호 복원에 대한 연구가 활발히 진행되고 있으며, 주로 블록 채널 부호화된 신호의 선형성에 대한 가우스-조던 소거(Gauss-Jordan elimination)를 적용하여 인터리버 파라미터를 추정한다. 그러나 가우스-조던 소거를 이용할 때 추정하고자 하는 인터리버의 주기가 커질수록 그 주기의 제곱배 이상의 연속적인 데이터가 필요하게 된다. 본 논문에서 제안하는 알고리즘은 기존의 인터리버 파라미터 추정 알고리즘에서 필요로 했던 입력 데이터 수의 15%만을 이용하며, 추정에 필요한 데이터를 충분히 확보하지 못했을 경우에도 적용이 가능하다. 또한 제안하는 알고리즘의 임의 신호 생성에 적용된 채널 부호화와 인터리버의 특징을 이용하면 기존의 알고리즘에서 분석해야 했던 인터리버 주기의 개수를 80% 가까이 줄일 수 있으며 인터리버의 종류와 행렬 크기뿐만 아니라 해당 채널부호화의 종류까지 추정 가능하다. Recently, much research on blind estimation of the interleaver parameters has been performed by using Gauss-Jordan elimination to find the linearity of the block channel code. When using Gauss-Jordan elimination, the input data to be calculated needs to run as long as the square multiple of the number of the interleaver period. Thus, it has a limit in estimating the interleaver parameters with insufficient input data. In this paper, we introduce and analyze an estimation algorithm which can estimate interleaver parameters by using only 15 percent of the input data length required in the above algorithm. The shorter length of input data to be calculated makes it possible to estimate the interleaver parameters even when limited data is received. In addition, a 80 percent reduction in the number of the interleaver period candidates increases the efficiency of analysis. It is also feasible to estimate both the type and size of the interleaver and the type of channel coding.

Universal Denoising for the Finite-Input General-Output Channel

We consider the problem of reconstructing a finite-alphabet signal corrupted by a known memoryless channel with a general output alphabet. The goodness of the reconstruction is measured by a given loss function. We (constructively) establish the existence of a universal (sequence of) denoiser(s) attaining asymptotically the optimum distribution-dependent performance for any stationary source that may be generating the noiseless signal. We show, in fact, that there is a whole family of denoiser sequences with this property. These schemes are shown to be universal also in a semistochastic setting, where the only randomness assumed is that associated with the channel noise. The scheme is practical, requiring O(n/sup 1+/spl epsiv//) operations (for any /spl epsiv/>0) and working storage size sublinear in the input data length. This extends recent work that presented a discrete universal denoiser for recovering a discrete source corrupted by a discrete memoryless channel (DMC).

Universal discrete denoising: known channel

A discrete denoising algorithm estimates the input sequence to a discrete memoryless channel (DMC) based on the observation of the entire output sequence. For the case in which the DMC is known and the quality of the reconstruction is evaluated with a given single-letter fidelity criterion, we propose a discrete denoising algorithm that does not assume knowledge of statistical properties of the input sequence. Yet, the algorithm is universal in the sense of asymptotically performing as well as the optimum denoiser that knows the input sequence distribution, which is only assumed to be stationary. Moreover, the algorithm is universal also in a semi-stochastic setting, in which the input is an individual sequence, and the randomness is due solely to the channel noise. The proposed denoising algorithm is practical, requiring a linear number of register-level operations and sublinear working storage size relative to the input data length.

Minimum data requirements for parameter estimation of stochastic weather generators

CR Climate Research Contact the journal Facebook Twitter RSS Mailing List Subscribe to our mailing list via Mailchimp HomeLatest VolumeAbout the JournalEditorsSpecials CR 25:109-119 (2003) - doi:10.3354/cr025109 Minimum data requirements for parameter estimation of stochastic weather generators Afshin Soltani1,*, Gerrit Hoogenboom2 1Department of Agronomy and Plant Breeding, Gorgan University of Agricultural Sciences, Gorgan, Iran 2Department of Biological and Agricultural Engineering, The University of Georgia, Griffin, Georgia 30223, USA *Email: asoltani_99@yahoo.com ABSTRACT: Long-term daily weather data are commonly required for the application of simulation models in agricultural systems. The objective of this study was to evaluate the impact of the length of input weather data on the quality of generated weather data and to determine the minimum data required for an accurate estimation of the climate coefficients for a weather generator. Five locations in Iran with contrasting climates were selected for this study. The WGEN and SIMMETEO weather generators were parameterized using 5, 10, 15, 20 and 30 yr of weather data as the base period (BP), and then 30 yr daily weather data sets were generated corresponding to each BP. While WGEN requires daily weather data for parameter estimation, SIMMETEO uses monthly summaries. The quality of the generated weather was measured as percentage significant differences between observed and generated data. Statistical tests were conducted, including t- and F-tests, to compare differences between generated weather data versus 30 yr historical weather data. The results showed that the number of years required to obtain generated data that were similar to observed data was a function of the weather generator and the weather variable. WGEN was more sensitive to the amount of input data than SIMMETEO. In 8 of the 14 cases WGEN required a specific minimum amount of data to be efficient in weather generation versus 6 of the 14 cases for SIMMETEO. There was a correlation between generator performance and its minimum data requirement. For the cases where the generators showed a good performance, i.e. low-percentage significant differences between observed and generated data, a specific minimum number of years was required. For generating precipitation, a smaller number of years was required than for generating temperature. Based on the results from this study, it can be concluded that at least 15 yr of input data are needed for WGEN and SIMMETEO to obtain generated sequences with statistical characteristics similar to the observed data. However, a greater length of input data may lead to an improved set of generated data as shown through more stable generated data. KEY WORDS: Weather generation · Weather data · Climate · Simulation models · Decision support systems Full text in pdf format PreviousNextExport citation RSS - Facebook - Tweet - linkedIn Cited by Published in CR Vol. 25, No. 2. Online publication date: December 05, 2003 Print ISSN: 0936-577X; Online ISSN: 1616-1572 Copyright © 2003 Inter-Research.

Borehole electrical resistivity modeling using neural networks

A neural network approach has been applied to model downhole resistivity tools, i.e., to generate a synthetic tool response for a given earth resistivity model. The microlaterolog (MLL), shallow dual laterolog (DLLs), and deep dual laterolog (DLLd) tools are modeled using neural networks to demonstrate this approach. Efforts have been made to select various neural network parameters, including the type of neural network, the length of input data for training, the number of hidden nodes, and the number of training samples. A modular neural network (MNN) has been selected because it can facilitate the training and prediction of tool responses in formations with large resistivity variations. The input data for training are taken to be the model formation resistivity values sampled over a depth window. The window length is chosen based on the tool lengths. Three different window lengths are used for experiments: 6.1, 9.1, and 30.5 m. We found the longer window lengths generally have higher modeling accuracy for the three different types of logging tools. The number of hidden nodes needed to yield satisfactory training and prediction data varies from 8 to 25, depending on the type of tool and the window length. Up to 30 000 training samples have been collected to train the MNN. Our modeling examples show that the trained MNN can achieve about 90% accuracy for the MLL log response and about 83% accuracy for the DLLs and DLLd responses. The modeling errors can be described roughly with a Gaussian distribution.