LECTOR Technique Research Articles

Design and implementation of a Low power Adder Circuit Using LECTOR Technique

This work implements a 1-bit FA circuit with the CMOS logic with XOR-XNOR combinations. For sum and carry, pass transistors are used to generate the output by combining with XOR, XNOR and CMOS design, and the optimised full adder is implemented with the help of LECTOR technique to control the leakage power. As scaling of CMOS technology has shown improvement in the speed but the leakage power are left to act as major effect. low power VLSI is a new discipline in which high power consumption is becoming an important criteria. But when refers to battery life, high power dissipation is not recommended for device applications. It affects performance, raises cooling expenses, and shortens battery capacity. The switching, dynamic and leakage power changes the inputs significantly. There are several typical reduction strategies available to lower the energy of circuits. By implementing the reduced FA with the leakage power control technique the number of transistors reduced than the normal full adder. The proposed design has static and total power of 5.08nw and 8.33uw for XNOR and for XOR of 12.36nw and 8.56uw. A FA is designed using these technique the obtained results for static and total power are 12.38uw 8.58uw. For the above circuits, a comparison of various static and total power dissipations is conducted. CADENCE-VIRTUOSO is used to simulate circuits using 90nm technology with a 1.2V power supply.

Implementation of three stage comparator using a modified latch with sustainable resources

In this paper, the current study uses a lector technique to modify the latch. The Lector approach is one of the top low-power methods for IC technologies. The locking mechanism is the third stage in our proposed design for a three-stage comparator. The lector approach is used for the three-stage comparator circuit in this case and its modified version. Pre-amplifier stages are the first two levels. The improved performance of this comparator circuit uses two sets of complementary biased two-stage preamplifiers. The traditional three-stage amplifier decreased the latency, while the modified version of the modified three-stage amplifier focused on the kickback noise. The proposed design of this three-stage comparator, which employs a lector approach, concentrates mainly on lower consumption. Tanner EDA was used to build and simulate this complete schematic. Materials having a lesser environmental effect are chosen, such as those that use fewer resources or are simpler to recycle after a product’s lifespan and sustainability.

Design of energy efficient domino logic circuit using lector technique

ABSTRACT Calculating power and delay in VLSI circuits are two main challenges in designing CMOS VLSI circuits. The manuscript proposes a lector technique-based foot-driven stack transistor domino logic for power and delay reduction. The lector technique uses two leakage-controlled transistors, PMOS and NMOS. The gate terminal of PMOS is connected to the source of NMOS, and the gate terminal of NMOS is connected to the source of PMOS. NMOS transistor N5 is used in the proposed circuit, driven by a dynamic node, which helps to reduce the power. This manuscript uses the proposed technique to design a buffer, two-input – AND gate, OR gate, and XOR gate circuits. The logic gates are simulated on the gpdk 45 nm cadence virtuoso software tool. The simulation result shows that the proposed domino logic circuit significantly reduces power, delay, energy, and leakage current. Monte Carlo analysis is performed to study the mean and standard deviation of the proposed circuit with 1000 samples.

A SMART DESIGN OF A MULTI-DIMENSIONAL ANTENNA TO ENHANCE THE MAXIMUM SIGNAL CLUTCH TO THE ALLOWABLE STANDARDS IN 5G COMMUNICATION NETWORKS

At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell. Since the operating range of 5G communication networks is the same as that of the previous generation, there are no difficulties in using these antennas on 5G communication networks. For any technology, the use of antennas makes it possible to bring data rates closer to maximum values. The new technology that uses separate receivers and transmitters on the same frequency band has further increased the speed of receiving and transmitting data. The design of the existing 4G modem provides for the use of antenna technology. The proposed model provides the construction of a multidimensional antenna. The other passive devices it has a one-way direction, which increases the received signal and reduces the amount of interference from the sides to the back. Therefore, the proposed model possible to increase the signal level to acceptable values, even at unstable reception levels thereby increasing the speed of receiving and transmitting the information. The undoubted advantage of panel antennas is their low cost and exceptional reliability. There is practically nothing in the design that can be broken even when falling from a great height. The only weak point is the high-frequency cable, which can break at the point where it enters the case. To extend the life of the device, the cable must be securely connected.

Design of half adder using integrated leakage power reduction techniques

The necessity for the development of compact, portable, and reliable electronic devices of enhanced speed and efficiency has prompted the scaling of CMOS devices to be indispensable. However, the benefit of scaling CMOS devices comes at the cost of increased leakage current in circuits. The variance in power consumption by these circuits incites detrimental impacts on the operational characteristics of the entire device. So, in this work, a novel leakage power reduction technique obtained by combining the Leakage Control Transistor (LECTOR) approach and drain gating approach is proposed. Both these subthreshold leakage minimization approaches are prominently used in Complementary Metal Oxide Semiconductor (CMOS) devices for curtailing the leakage power. The effectiveness of the proposed Integrated Drain Gating Lector (IDGL) technique in mitigating the leakage power is ascertained by designing a half adder circuit. Hence the overall leakage power is of 3.16nW & delay 69.12 µs in 180 nm technology, and in low scale technology of 90 nm the same leakage power decline to 2.19nW & delay is 65.45 µs.

Leakage reduction technique for nano-scaled devices

PurposeThe purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.Design/methodology/approachBecause of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.FindingsThis study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.Originality/valueAll the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

WITHDRAWN: Comparative analysis on low power SRAMs

Abstract Static Random Access memory (SRAM) has become an important role due to their low access time and storage capacity. The Static Random Access Memory (SRAM) has a significant impact on the overall power consumption and energy efficiency. The leakage power in SRAM is one of the most significant problems when technology node is scaling down. The main concept of this survey is to compare various Low power SRAMs based on their power consumption as well as delay in the SRAM. Different types of power reduction techniques like power gating, sleepy keeper leakage control transistor technique (SK-LCT), Gated ground sleep logic, LECTOR and MTCMOS techniques, etc.. are applied to the SRAM to reduce the power consumption and various parameters like leakage power, delay, speed and Static Noise Margin (SNM) in different EDA tools like Tanner, Cadence, Silvaco TCAD etc., This comparative analysis conclude that forced sleep technique is reduces power consumption and up to 40% and 43% respectively when compared with other technique. This comparative analysis helps the designer and researchers to get the overview of all the available techniques with their results, so they can choose the best techniques based on their specific requirements.

Modified LECTOR Technique for Level Shifters

Static power dissipation is a major problem in CMOS circuits and this is due to the increase in sub threshold leakage current which is the effect of voltage scaling and also leading to reducing the threshold voltage. Here we propose Lector technique to reduce the leakage current and at the same time it will not increase the dynamic power dissipation. Two leakage control transistors of which one is p-type and the other one is n-type were introduced into the logic gate. The source of one transistor controls the gate terminal of the other transistor. For any combination of input one of the two leakage control transistors will be near to its cutoff voltage by this the leakage currents can be minimized as the path resistance to ground will increase. For both idle and active states of circuit the proposed Lector technique is applicable which will result in more leakage reduction when compared to remaining techniques used for leakage reduction and it will also out pass the limitations Occurred due to the implementation of other power and delay reduction techniques. Experimental results indicate a delay is reduced by 50.3% and power is reduced by 94.4% for proposed level shifter circuits.

Estimation of power and delay in CMOS circuits using LCT

<p>With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors(HTLCT). In this paper, we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The estimation of power and delay will be discussed using LCT’s and HTLCT’s</p>

Estimation of Power and Delay in CMOS Circuits using Leakage Control Transistor

Abstract With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors (HTLCT).In this paper; we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The proposed technique overcomes the limitations posed by the existing methods for leakage reductions an average leakage reductions is 82.5%.The estimation of power and delay will be discussed using LCT’s and HTLCT’s.

Design of low power johnson counter using lector technique using 50nm technology

Design of low power johnson counter using lector technique using 50nm technology

Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

This work impacts on the huge potential of FinFET technology, which can replace bulk MOS below 32 nm. Here, two new techniques are introduced to mitigate leakage power as leakage controlling pass transistor P-type LCPT (P) and leakage controlling pass transistor N-type LCPT(N) techniques. Some existing and proposed circuits are simulated in high performance (HP) and lower standby power FinFET library at 20, 16, 14, 10, and 7 nm by using the Berkley predictive technology module for the sake of comparison. Simulation results of a two-input NAND gate using proposed techniques at 10 MHz frequency using FinFET technology saves a maximum of leakage power using LCSPT (P) at input vector 11 of 98.90% compared with a conventional NAND gate. Similarly LCSPT (N) saves a maximum of leakage power of 98.44% at 10 input vectors compared with LECTOR technique at 20 nm in HP model. Also maximum saving of dynamic power by LCSPT (P) is 59.6% at 14 nm as compared to conventional NAND gate.

Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read and Write Enable

Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read and Write Enable

COMPARATIVE ANALYSIS OF LECTOR AND STACK TECHNIQUE TO REDUCE THE LEAKAGE CURRENT IN CMOS CIRCUITS

CMOS is the latest technology available in today’s world. And the biggest advantage of this technology is it does not consume any power. So the total power consumption is dependent on its leakage power. Since leakage exists in the circuit even if it is in stand by state i.e. the state in which gate of the circuit is not getting power supply. So the power loss in the circuit is high. And that’s why our major concern is to reduce the leakage current in the circuit. Varieties of different techniques are available to reduce the leakage current and still continue to derive more, better techniques. In this paper two different techniques LECTOR and STACK technique which are based on the same principle have been comparatively analyzed.

LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY

In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage current in the path. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques.