Leakage Power Reduction Research Articles

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

As the development of deep-submicron and nano-technology, leakage power minimisation becomes as important as dynamic power reduction in IC design. In order to achieve low-power state assignment for finite-state machine (FSM) synthesis, a multi-population genetic algorithm (MPGA)-based state assignment method is proposed. MPGA consists of an outer-loop and a set of inner-GAs. In MPGA, inner-GA is a local search component for finding low-power state assignment. Selection, crossover and mutation are used to perform variations on individuals. Cost function is defined based on power dissipation formulation of complementary metal oxide semiconductor (CMOS) gate for dynamic power and leakage power estimation. The outer-loop is used to optimise the parameters of inner-genetic algorithm (GA) through population variation schema, intra-specific competition and newborn. Twenty-three FSMs that were commonly used as benchmarks are employed to test the effectiveness of MPGA and compare different state assignment methods. Experimental results show MPGA achieves a significant improvement over the previous publications both on dynamic power and leakage power reduction in most benchmarks.

An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes

With the aggressive downscaling of process technologies and the importance of battery-powered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In addition, the traditional bulk CMOS technologies face significant challenges related to short-channel effects and process variations. FinFET devices have attracted a lot of attention as an alternative to bulk CMOS in sub-32nm technology nodes. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near- and super-threshold ( $V_T$ ) operation regimes. The impacts of cell-level and transistor-level Gate-Length Biasing (GLB) on circuit speed and leakage power are studied using a 7 nm FinFET technology.

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

New Leakage Reduction Techniques for FinFET Technology with Its Application

This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32[Formula: see text]nm technology node at 25[Formula: see text]C and 110[Formula: see text]C temperatures. The proposed techniques are applied on standard and benchmark circuits, then these circuits are implemented on FinFET technology in short-gate (SG) and LP modes at 10[Formula: see text]MHz frequency. Simulation results show that the maximum reduction in leakage power by the proposed technique DGPT for two-input NAND gate is 99.34% in SG mode and in LP mode it is 99.83% at 25[Formula: see text]C. DGNT technique gives the maximum saving in leakage power consumption of 97.17% in SG mode and in LP mode a maximum saving of 95.10% at 25[Formula: see text]C is achieved. Similarly, DGNPT saves 99.34% in SG mode and in LP mode it saves 99.90% leakage power at 25[Formula: see text]C with respect to conventional gates. The proposed techniques are also applied on different benchmark circuits and the results are validated. As an application of the proposed techniques, NAND gate is modified accordingly and it is used in 1-bit and 2-bit full-adder circuits.

Comparative analysis of SRAM cell with leakage power reduction approaches

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

Sleep signal controlled footless domino circuit for low leakage current

PurposeThis paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.Design/methodology/approachIn the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.FindingsThe authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.Originality/valueThe proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips

The leakage power of decaps occupies a large portion of total chip leakage power. In this paper we propose an approximate approach to estimate the amount of the required “on” capacitance of each decap at runtime to achieve runtime decap modulation in multicore chips, and further develop two techniques (incremental calculation and sparsification) to improve the approximate approach. Results on a set of benchmarks show that our approach can achieve about 45% saving in decap leakage on average, and the approximate approach can further reduce the computation cost by up to 22× with accuracy loss of less than 1%.

A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications

In this work, a 9T subthreshold SRAM cell is proposed with the reduced leakage power and improved stability against the PVT variations. The proposed cell employs the read decoupling to improve the read stability, and the partial feedback cutting approach to control the leakage power with improved read/write ability. The incorporated stacking effect further improves the leakage power. The simulated leakage power for the proposed cell is 0.61×, 0.49×, 0.80× and 0.55×, while the read static noise margin (RSNM) is 2.5×, 1×, 1.05× and 0.96×, write static noise margin (WSNM) 0 is 1.5×, 1.8×, 1.68× and 1.9× and WSNM 1 is 0.95×, 1.2×, 1.05×, and 1.2× at 0.4 V when compared with the conventional 6T and state of arts (single ended 6T, PPN based 10T and data aware write assist (DAWA) 12T SRAM architectures) respectively. The minimum supply voltage at which this cell can successfully operate is 220 mV. A 4 Kb memory array has also been simulated using proposed cell and it consumes 0.63×, 0.67× and 0.63× less energy than 6T during read, write 1 and write 0 operations respectively for supply voltage of 0.3 V.

A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation

This paper presents a new dual Vt 8T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation (WARI). Also a faster write back scheme is proposed for the half selected cells. A high Vt device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin (RSNM) due to the bit-line isolation during the read. Static noise margins for data read (RSNM), write (WSNM), read delay, write delay, data retention voltage (DRV), leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells, which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.

A Review on Various Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS VLSI Circuits

A Review on Various Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS VLSI Circuits

A Unified Scheduling Approach for Power and Resource Optimization With Multiple $V_{\mathrm{ dd}}$ or/and $V_{\mathrm{ th}}$ in High-Level Synthesis

In this paper, we focus on the low-power scheduling problem with multiple threshold and/or supply voltage technologies in high-level synthesis. We propose a unified scheduling approach which is applicable to various optimization problems, including: 1) dynamic power and resource usage co-optimization; 2) leakage power optimization; and 3) dynamic power and leakage power co-optimization. To deal with different objectives with high flexibility, three problems are divided into two common subproblems including delay assignment and resource density variance minimization, then a vertex potential-based mobility allocation model is proposed to solve two subproblems simultaneously. Experimental results show that, for dynamic power and resource co-optimization, our scheduling approach produces optimum solutions for all six benchmarks with 15 groups of data; for leakage power optimization it also greatly excels the latest existing work, by 20% leakage power reduction and 52 times speedup. Besides, for dynamic and leakage power co-optimization, the Pareto solutions are studied.

2017 International Symposium on Computer Architecture Influential Paper Award

This article discusses the 2017 ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award, which was given to the 2002 ISCA paper, “Drowsy Caches: Simple Techniques for Reducing Leakage Power.”

A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

Design of Low-Power High-Performance FinFET Standard Cells

With the leakage power becoming a most important concern in deep sub-micron designs, the advent of FinFET offers promising options due to its superior electrical properties and design flexibility. To support the VLSI digital system design flow based on the standard cells in FinFET, the building method of optimized FinFET standard cells is proposed. This method is derived on the basis of jointly optimizing the back-gate voltages and the width to length ratio of the transistors in the stacked structure in each standard cell under the premise of maintaining the performance. By employing this design method, optimized standard cells are generated and form a low-power high-performance standard cell library. Simulation results of the standard cells designed with our proposed method demonstrate that the leakage power can be reduced by a factor of 47.99 at most while the worst-case delay can achieve a maximum reduction of 10.17%. Monte Carlo simulation results illustrate that the optimized cells can gain more dependability to process variations and environmental changes. The 16-bit ripple carry adder implemented with this optimized FinFET library can obtain a maximum leakage power reduction of 59.6% and a worst-case delay reduction of 21.8%.

P2NoC: Power- and Performance-aware NoC Architectures for Sustainable Computing

Communication performance over distant nodes and high power consumption are major challenges for efficient Network-on-Chip (NoC) architectures. Wireless NoCs, by augmenting wired topologies with low latency wireless links, overcome performance limitations of conventional NoCs. However, NoC routers and Wireless Interfaces (WIs) consume significant amount of leakage power. The usage of routers in NoC is application dependent and for most applications, performance requirement can be achieved without operating all resources all the time. Similarly, WIs transmitting data over shared channel can be selectively turned off when they are not active. Exploiting these, we propose Power- and Performance-aware NoC (P2NoC) architecture that power gates router elements and WIs depending upon their utilization to reduce leakage power. P2NoC works based on hybrid two-level router utilization estimate; pre-computed and runtime to provide coarse and fine estimate of utilization to maximize power saving while keeping overheads and performance impact to a minimum. We also propose deadlock-free seamless bypass routing strategy with P2NoC to avoid adverse impacts of power gating. P2NoC saves up to 92.20% and 68.23% of leakage power in base and hybrid routers respectively with only 7% area overhead. Based on utilization, P2NoC also reduces total average packet energy consumption by 49% with negligible performance degradation. The proposed solution provides a flexible sustainable computing platform that can be optimized for a wide range of application scenarios.

A Modified Signal Feed-Through Pulsed Flip- Flop for Low Power Applications

AbstractIn this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.

Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

This work impacts on the huge potential of FinFET technology, which can replace bulk MOS below 32 nm. Here, two new techniques are introduced to mitigate leakage power as leakage controlling pass transistor P-type LCPT (P) and leakage controlling pass transistor N-type LCPT(N) techniques. Some existing and proposed circuits are simulated in high performance (HP) and lower standby power FinFET library at 20, 16, 14, 10, and 7 nm by using the Berkley predictive technology module for the sake of comparison. Simulation results of a two-input NAND gate using proposed techniques at 10 MHz frequency using FinFET technology saves a maximum of leakage power using LCSPT (P) at input vector 11 of 98.90% compared with a conventional NAND gate. Similarly LCSPT (N) saves a maximum of leakage power of 98.44% at 10 input vectors compared with LECTOR technique at 20 nm in HP model. Also maximum saving of dynamic power by LCSPT (P) is 59.6% at 14 nm as compared to conventional NAND gate.

Minimum Implant Area-Aware Placement and Threshold Voltage Refinement

Threshold voltage assignment is a very effective technique to reduce leakage power consumption in modern integrated circuit design. As feature size continues to decrease, the layout constraints [called minimum implant area (MinIA) constraints] on the implant area, which determines the threshold voltage of a device, are becoming increasingly difficult to satisfy. It is necessary to take these constraints into consideration during the placement stage. In this paper, we propose to resolve the MinIA constraint violations of a given placement by performing simultaneous detailed placement and threshold voltage refinement. We first present an optimal and efficient mixed integer-linear programming (MILP)-based algorithm to handle intrarow MinIA constraints. We then extend the MILP-based algorithm to handle both inter-row and intrarow MinIA constraints. Both of our algorithms guarantee to fix all MinIA constraint violations. Experimental results demonstrate that our algorithms only perturb the original placement and threshold voltage assignment solutions minimally to eliminate all violations and are fast in practice.

Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM

In recent years, much emphasis is given for low power memory design by reducing leakage power. Carbon nanotube field effect transistor (CNTFET) based static random access memory (SRAM) provides better stability along with low static power consumption due to variable bandgap and threshold voltage as function of diameter. Electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET) accounts for much low leakage current and hence can be used for low power SRAM design. This paper proposes a novel design of ED-SBCNTFET based low power SRAM which consists of additional polarity gates. 6-T SRAM cell is designed and simulated in HSPICE for both conventional CNTFET and ED-SBCNTFET. SRAM performance is analyzed on the basis of various figures of merit i.e. stability and power dissipation. ED-SBCNTFET SRAM shows advantage of low power over conventional CNTFET SRAM without loss of stability. Furthermore, SRAM is designed for smaller diameter which gives ultra low power cell with minute change in stability. Lastly dual chirality scheme is implemented and analyzed for ED-SBCNTFET 6-T SRAM cell.

Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.