New Leakage Reduction Techniques for FinFET Technology with Its Application

Abstract

This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32[Formula: see text]nm technology node at 25[Formula: see text]C and 110[Formula: see text]C temperatures. The proposed techniques are applied on standard and benchmark circuits, then these circuits are implemented on FinFET technology in short-gate (SG) and LP modes at 10[Formula: see text]MHz frequency. Simulation results show that the maximum reduction in leakage power by the proposed technique DGPT for two-input NAND gate is 99.34% in SG mode and in LP mode it is 99.83% at 25[Formula: see text]C. DGNT technique gives the maximum saving in leakage power consumption of 97.17% in SG mode and in LP mode a maximum saving of 95.10% at 25[Formula: see text]C is achieved. Similarly, DGNPT saves 99.34% in SG mode and in LP mode it saves 99.90% leakage power at 25[Formula: see text]C with respect to conventional gates. The proposed techniques are also applied on different benchmark circuits and the results are validated. As an application of the proposed techniques, NAND gate is modified accordingly and it is used in 1-bit and 2-bit full-adder circuits.