Leakage Current Research Articles

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Characteristics of Vertical Transistors on a GaN Substrate Fabricated via Na‐Flux Method and Enlargement of the Substrate Surpassing 6 Inches

The Na‐flux method is expected to be a key GaN growth technique for obtaining ideal bulk GaN crystals. Herein, the structural quality of the latest GaN crystals grown using the Na‐flux method and, for the first time, the characteristics of a vertical transistor fabricated on a GaN substrate grown using this method are discussed. Vertical transistors exhibit normally off operation with a gate voltage threshold exceeding 2 V and a maximum drain current of 3.3 A during the on‐state operation. Additionally, it demonstrates a breakdown voltage exceeding 600 V and a low leakage current during off‐state operation. It is also described that the variation in the on‐resistance can be minimized using GaN substrates with minimal off‐angle variations. This is crucial for achieving the large‐current chips required for future demonstration of actual devices. In addition, the reverse I–V characteristics of the parasitic p–n junction diode (PND) structures indicate a reduction in the number of devices with a significant leakage current compared to commercially available GaN substrates. Finally, a circular GaN substrate with a diameter of 161 mm, surpassing 6 inches, grown using the Na‐flux method is demonstrated, making it the largest GaN substrate aside from those produced through the tiling technique.

Nondefective Vacancy Enhanced Resistive Switching Reliability in Emergent van der Waals Metal Phosphorus Trisulfide-Based Memristive In-Memory Computing Hardware.

Two-dimensional-material-based memristors are emerging as promising enablers of new computing systems beyond von Neumann computers. However, the most studied anion-vacancy-enabled transition metal dichalcogenide memristors show many undesirable performances, e.g., high leakage currents, limited memory windows, high programming currents, and limited endurance. Here, we demonstrate that the emergent van der Waals metal phosphorus trisulfides with unconventional nondefective vacancy provide a promising paradigm for high-performance memristors. The different vacancy types (i.e., defective and nondefective vacancies) induced memristive discrepancies are uncovered. The nondefective vacancies can provide an ultralow diffusion barrier and good memristive structure stability giving rise to many desirable memristive performances, including high off-state resistance of 1012 Ω, pA-level programming currents, large memory window up to 109, more than 7-bit conductance states, and good endurance. Furthermore, a high-yield (94%) memristor crossbar array is fabricated and implements multiple image processing successfully, manifesting the potential for in-memory computing hardware.

Advanced Optoelectronic Modeling and Optimization of HTL-Free FASnI3/C60 Perovskite Solar Cell Architecture for Superior Performance.

In this study, a novel perovskite solar cell (PSC) architecture is presented that utilizes an HTL-free configuration with formamide tin iodide (FASnI3) as the active layer and fullerene (C60) as the electron transport layer (ETL), which represents a pioneering approach within the field. The elimination of hole transport layers (HTLs) reduces complexity and cost in PSC heterojunction structures, resulting in a simplified and more cost-effective PSC structure. In this context, an HTL-free tin HC(NH2)2SnI3-based PSC was simulated using the solar cell capacitance simulator (SCAPS) within a one-dimensional framework. Through this approach, the device performance of this novel HTL-free FASnI3-based PSC structure was engineered and evaluated. Key performance parameters, including the open-circuit voltage (Voc), short-circuit current density (Jsc), fill factor (FF), power conversion efficiency (PCE), I-V characteristics, and quantum efficiency (QE), were systematically assessed through the modulation of physical parameters across various layers of the device. A preliminary analysis indicated that the HTL-free configuration exhibited improved I-V characteristics, with a PCE increase of 1.93% over the HTL configuration due to improved electron and hole extraction characteristics, reduced current leakage at the back contact, and reduced trap-induced interfacial recombination. An additional boost to the device's key performance parameters has been achieved through the further optimization of several physical parameters, such as active layer thickness, bulk and interface defects, ETL thickness, carrier concentration, and back-contact materials. For instance, increasing the thickness of the active layer PSC up to 1500 nm revealed enhanced PV performance parameters; however, further increases in thickness have resulted in performance saturation due to an increased rate of hole-electron recombination. Moreover, a comprehensive correlation study has been conducted to determine the optimum thickness and donor doping level for the C60-ETL layer in the range of 10-200 nm and 1012-1019 cm-3, respectively. Optimum device performance was observed at an ETL-C60 ultra-thin thickness of 10 nm and a carrier concentration of 1019 cm-3. To maintain improved PCEs, bulk and interface defects must be less than 1016 cm-3 and 1015 cm-3, respectively. Additional device performance improvement was achieved with a back-contact work function of 5 eV. The optimized HTL-free FASnI3 structure demonstrated exceptional photovoltaic performance with a PCE of 19.63%, Voc of 0.87 V, Jsc of 27.86 mA/cm2, and FF of 81%. These findings highlight the potential for highly efficient photovoltaic (PV) technology solutions based on lead-free perovskite solar cell (PSC) structures that contribute to environmental remediation and cost-effectiveness.

The impact of S vacancies on the modulation of the work function and Schottky barrier at the Au/MoS2 interface

The S vacancy at metal/MoS2 interface plays a much important role than the semiconductor itself. In this work, the influence of different configurations of S vacancy concentrations on the effective work function and band structure of the Au/MoS2 interface has been investigated systematically using first-principles calculations. The study specifically explores the effective work function of the Au/MoS2 interface, the deviation of interface effects from the vacuum work function, and the dipole moment caused by interface charge transfer. The results reveal that the electronic work function of Au/MoS2 increases with the increase in S vacancy concentration, but the rate of increase tends to slow down with higher S concentrations. The variation in the effective work function of the Au/MoS2 interface may be attributed to the presence of S vacancies and the exposure of Mo atoms. S vacancies lead to a reduction in the Schottky barrier, resulting in increased leakage current. The Fermi pinning caused by S vacancy concentration and location is also observed. The results obtained in this study can serve as a theoretical foundation for applications in electronic devices that rely on metal/MoS2 contact.

Leakage detection applied to the Da Hedong Reservoir dam (China) based on the flow-field fitting method

Detecting leakage in concrete gravity dams presents a formidable challenge. The flow-field fitting (FFF) method is used to identify leaks in China’s Da Hedong Reservoir dam. We develop vertical- and horizontal-gradient approaches based on the transmitted signal electrical field. A plastic frame is developed to allow the probe to measure horizontal gradients. We determine the exact location of leaks at the reservoir’s bottom and upstream face, respectively, assuming that current leakages are located in hydraulic leakage zones. Numerical experiments and water pressure tests reveal that the conductive silt layer beneath the reservoir can lower the response of the potential values at the leakage inlet, and the effect of the silt layer should be considered and not ignored when interpreting measured data. In addition, with regard to the principle of superposition, the contribution associated with metal pipes in the dam body can be roughly determined by subtracting it from the original potential field data, thereby aiding in locating leaks around the metal pipes. In addition, the FFF measurements from the reservoir’s bottom also confirm the position of existing faults in the substratum at the reservoir site. Last, the results of the FFF method are tested against supporting evidence, such as ground penetrating radar and water pressure tests. In conclusion, these independent data confirm the effectiveness of the FFF method for leakage localization in the concrete gravity dam.

Effect of rapid thermal annealing on DC performance of Mg0.30Zn0.70O/Cd0.15Zn0.85O MOSHFET

This study focuses on a cost-effective method for fabrication of a metal oxide semiconductor-heterostructure field effect transistor (MOSHFET) based on MgZnO/CdZnO (MCO) using dual ion beam sputtering (DIBS), in contrast to the more expensive epitaxial growth system. The MOSHFETs developed in this research exhibit notable characteristics, such as a substantial two-dimensional electron gas (2DEG) transconductance (∼2.6 mS), a high ION/IOFF response ratio in the order of 108, and minimal gate leakage current. Furthermore, we explore the impact of rapid thermal annealing (RTA) on the drain current at various temperatures (600 °C and 800 °C). The results indicate a fourfold improvement in drain current compared to unannealed conditions, primarily attributed to reduced contact resistance and no degradation in term of MgZnO/CdZnO structure. Additionally, an analysis of post-RTA treatment under a nitrogen (N2) atmosphere on gate leakage current is presented. The investigation spans temperatures ranging from 400 °C to 800 °C, revealing that above 600 °C (gate leakage at 400 °C–600 °C is around ∼10−9 A), gate leakage in HFET is augmented by one order of magnitude (∼10−8 A) due to a phase change in the dielectric. These findings underscore the feasibility of DIBS-grown MCO MOSHFETs as an economical solution for the mass production of switching devices and sensors.

Stability Study of Synthetic Diamond Using a Thermally Controlled Biological Environment: Application towards Long-Lasting Neural Prostheses.

This paper demonstrates, for the first time, the stability of synthetic diamond as a passive layer within neural implants. Leveraging the exceptional biocompatibility of intrinsic nanocrystalline diamond, a comprehensive review of material aging analysis in the context of in-vivo implants is provided. This work is based on electric impedance monitoring through the formulation of an analytical model that scrutinizes essential parameters such as the deposited metal resistivity, insulation between conductors, changes in electrode geometry, and leakage currents. The evolution of these parameters takes place over an equivalent period of approximately 10 years. The analytical model, focusing on a fractional capacitor, provides nuanced insights into the surface conductivity variation. A comparative study is performed between a classical polymer material (SU8) and synthetic diamond. Samples subjected to dynamic impedance analysis reveal distinctive patterns over time, characterized by their physical degradation. The results highlight the very high stability of diamond, suggesting promise for the electrode's enduring viability. To support this analysis, microscopic and optical measurements conclude the paper and confirm the high stability of diamond and its strong potential as a material for neural implants with long-life use.

Exploring tungsten-oxygen vacancy synergy: Impact on leakage characteristics in Hf0.5Zr0.5O2 ferroelectric thin films

The recent discovery of ferroelectric properties in HfO2 has sparked significant interest in the fields of nonvolatile memory and neuromorphic computing. Yet, as device scaling approaches sub-nanometer dimensions, leakage currents present a formidable challenge. While tungsten (W) electrodes are favored over traditional TiN electrodes for their superior strain and interface engineering capabilities, they are significantly hampered by leakage issues. In this study, we elucidate a positive feedback mechanism attributable to W electrodes that exacerbates oxygen vacancy defects, as evidenced by density functional theory computations. Specifically, intrinsic oxygen vacancies facilitate the diffusion of W, which, in turn, lowers the formation energy of additional oxygen vacancies. This cascade effect introduces extra defect energy levels, thereby compromising the leakage characteristics of the device. We introduce a pre-annealing method to impede W diffusion, diminishing oxygen vacancy concentration by 5%. This reduction significantly curtails leakage currents by an order of magnitude. Our findings provide a foundational understanding for developing effective leakage suppression strategies in ferroelectric devices.

Controlled growth of uniform and dense perovskite layers on SnO2 via interface passivation by PbS quantum dots

AbstractFormamidinium lead iodide (FAPbI3) and SnO2 are a promising pair of halide perovskite and electron transport layer (ETL). However, FAPbI3 and SnO2 have inherent problems such as high crystallization temperature of FAPbI3 and surface defects of SnO2 like oxygen vacancies. They cause low crystallinity, non‐uniform grain growth, and more interface defects, leading to carrier recombination and leakage current. The passivation of the interface between FAPbI3 and SnO2 is an effective process to address these materials issues. Herein, a dual role of lead sulfide (PbS) quantum dots (QDs) in the interface passivation is explored. PbS QDs which are introduced to the interface between FAPbI3 and ETL, link to Sn‐dangling bonds of SnO2 ETLs and anchor the iodine atoms of FAPbI3. This changes considerably lower nonradiative recombination, achieve a better energetic alignment between ETL and PbI3, and facilitate electron extraction, leading to a power conversion efficiency of 21.66%.image

Optimization of Epitaxial Structures on GaN-on-Si(111) HEMTs with Step-Graded AlGaN Buffer Layer and AlGaN Back Barrier

Recently, crack-free GaN-on-Si growth technology has become increasingly important due to the high demand for power semiconductor devices with high performances. In this paper, we have experimentally optimized the buffer structures such as the AlN nucleation layer and step-graded AlGaN layer for AlGaN/GaN HEMTs on Si (111) substrate by varying growth conditions and thickness, which is very crucial for achieving crack-free GaN-on-Si epitaxial growth. Moreover, an AlGaN back barrier was inserted to reduce the buffer trapping effects, resulting in the enhancement of carrier confinement and suppression of current dispersion. Firstly, the AlN nucleation layer was optimized with a thickness of 285 nm, providing the smoothest surface confirmed by SEM image. On the AlN nucleation layer, four step-graded AlGaN layers were sequentially grown by increasing the Al composition from undermost layer to uppermost layer, meaning that the undermost one was close to AlN, and the uppermost was close to GaN, to reduce the stress and strain in the epitaxial layer gradually. It was also verified that the thicker step-graded AlGaN buffer layer is suitable for better crystalline quality and surface morphology and lower buffer leakage current, as expected. On these optimized buffer structures, the AlGaN back barrier was introduced, and the effects of the back barrier were clearly observed in the device characteristics of the AlGaN/GaN HEMTs on Si (111) substrate such as the transfer characteristics, output characteristics and pulsed I-V characteristics.

Bi compensation and poling process to enhance piezoelectric properties of BiFeO3-BaTiO3 lead-free piezoceramics

BiFeO3-BaTiO3 (BF-BT) ceramics are an excellent choice for high-temperature lead-free piezoelectric ceramic due to their high Curie temperature and good piezoelectric properties, but the volatilization of Bi leads to the formation of A-site cationic vacancies and oxygen vacancies, culminating in heightened leakage currents and detrimental effects on piezoelectric properties. In this study, a chemical composition of 0.70Bi(1+x)Fe0.97Al0.03O3-0.30BaTiO3 ceramics, abbreviated as B1+xFA-BT, where 0 ≤ x ≤ 0.05, were synthesized, with special attention on the effects of Bi compensation and poling process on their insulation and piezoelectric properties. Due to the coexistence of R-PC phases and low leakage current, B1+xFA-BT ceramics exhibit excellent piezoelectric properties and high Curie temperature, among which the B1.02FA-BT ceramic boasts optimal overall properties: d33 = 196 pC·N-1, TC = 480 °C, kp = 34%, θmax = 49.5° and Qm = 32, under optimal poling parameters Ep = 50 kV·cm-1 and Tp = 100 °C. The poling process is directly linked to the reorientation of domains, the redistribution of positive/negative space charge and the aggregation or injection of holes, which is achieved by tuning the poling field and temperature in a ceramic with optimal integrated piezoelectric properties. The poling process of BF-BT ceramics is significantly influenced by their leakage characteristics, which can have a significant impact on their overall performance. Optimizing electrical poling conditions and minimizing leakage current is crucial to achieving favorable piezoelectric properties in BF-BT ceramics with R-PC coexisting structures.

Classification modeling of valve internal leakage acoustic emission signals based on optimal wavelet scattering coefficients

In order to achieve acoustic emission detection in valve internal leakage, it is essential to extract features, and establish an accurate mathematical model. Current valve internal leakage acoustic emission signal (VILAES) classification models mostly rely on human experience for selecting features, resulting in low accuracy for small leakage conditions. This paper combines the wavelet scattering transform (WST), Relief-F algorithm and AdaBoost.M1 algorithm, and proposes to use the optimal wavelet scattering coefficients as features to establish the VILAES classification model accurately for small leakage. Firstly, the first three order wavelet scattering coefficients of the VILAES are automatically extracted using WST and are transformed into one-dimensional features. Secondly, the Relief-F algorithm is employed to select the optimal feature subset. Finally, the optimal wavelet scattering coefficients and pressures are used as inputs to establish a classification model for VILAES and achieve an accuracy over 96.80% for small leakage.

Robust PWM control scheme for switched-capacitor MLI with leakage current suppression in grid-connected renewable energy application

Typically, parasitic capacitances exist between the ground and the solar panel terminals in grid-connected PV systems. These parasitic capacitances provide a path for a leakage current, which leads to significant safety concerns, observable and seriously hazardous harmonic orders aligned with the injected grid current, and significant safety difficulties. In this research, a robust PWM controlling method that used competently in reducing the level of the leakage current and improving the power quality of a switched-capacitor Multilevel Inverter. This technique creates developed reference signals from the main signal to generate the switching scheme for the converter circuit. Additionally, the suggested control strategy only works with a small number of carrier signals, resulting in a quick system response and a simpler controller algorithm. Likewise, this controlling approach offers a stable way to maintain a constant output voltage in the suggested converter by adjusting the switching capacitors' voltages, which is not possible with traditional control techniques. MATLAB/Simulink is used to simulate the outcomes for both the suggested control approach and the traditional Phase Disposition (PD) PWM control method whereas the leakage current component reduces to 25 % compared to the captured component with the PDPWM. The simulation and the practical results based on the dSPACE-1103 hardware are quite similar.

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study.

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell-Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10-15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10-11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.

High-speed carbon nanotube photodetector based on a planarized silicon waveguide

The integration of silicon waveguides with low-dimensional materials with excellent optoelectronic properties can enable compact and highly integrated optical devices with multiple advantages for multiple fields. A carbon nanotube (CNT) photodetector integrated on the silicon waveguide has the potential to meet on-chip high-speed optical interconnection systems, based on the outstanding properties of CNTs such as picosecond-level intrinsic photoresponse time, high charge carrier mobility, broad spectral response, high absorption coefficient, and so on. However, the thermal stability of the device may be compromised due to the local suspension in the channel for the height difference between the WG and the substrate. Here, we report a low-cost and low-optical-loss method to achieve the planarized silicon waveguide. After that, the CNT photodetectors integrated on the original and planarized waveguide with asymmetric palladium (Pd)-hafnium (Hf) metal contacts are fabricated. The influence of this planarization method on the performance of devices is analyzed via comparing the dark leakage current, the leakage current rectification ratio (CRR), the series resistances (R S ), and the photoelectric response. Finally, a CNT photodetector based on the planarized waveguide with a photocurrent (Iph) ∼510.84nA, a photoresponsivity (R I ) ∼51.04mA/W, the dark current ∼0.389µA, as well as a 3 dB bandwidth ∼34GHz at the large reverse voltage −3V is shown.

Constructing Multi‐Functional Polymeric‐Termination Surface Enables High‐Performance Flexible Perovskite LEDs

AbstractFlexible perovskite light‐emitting diodes (f‐PeLEDs) have attracted increasing interest to realize true‐color, low‐cost, and light‐weight wearable optoelectronic and flexible display applications. However, their external quantum efficiency (EQE) and mechanical stability lag far behind because of the inherent surface and brittle issues of polycrystalline perovskite films. In this work, a multi‐functional polymeric‐termination surface of perovskite film is constructed for achieving efficient and mechanically stable f‐PeLEDs. It takes the roles to not only reduce defects through equipping coordination groups to improve emission properties, but also optimize film morphology and eliminate pinholes to solve the long‐standing issue of leakage current. Meanwhile, the polymeric‐termination surface with anchoring points and polymeric soft chains on perovskites demonstrates synergetic effects beyond the corresponding functional group‐only or polymer‐only strategies in reducing the Young's modulus and improving the mechanical flexibility. Ultimately, the record EQE of 22.1% and significantly enhanced mechanical stability of maintaining 82% of the initial performance after 2000 bending cycles with radius of 5 mm are achieved in pure‐green f‐PeLEDs. The work paves the way for the development of high‐performance flexible optoelectronic devices.

Etching-free pixel definition in InGaN green micro-LEDs

The traditional plasma etching process for defining micro-LED pixels could lead to significant sidewall damage. Defects near sidewall regions act as non-radiative recombination centers and paths for current leakage, significantly deteriorating device performance. In this study, we demonstrated a novel selective thermal oxidation (STO) method that allowed pixel definition without undergoing plasma damage and subsequent dielectric passivation. Thermal annealing in ambient air oxidized and reshaped the LED structure, such as p-layers and InGaN/GaN multiple quantum wells. Simultaneously, the pixel areas beneath the pre-deposited SiO2 layer were selectively and effectively protected. It was demonstrated that prolonged thermal annealing time enhanced the insulating properties of the oxide, significantly reducing LED leakage current. Furthermore, applying a thicker SiO2 protective layer minimized device resistance and boosted device efficiency effectively. Utilizing the STO method, InGaN green micro-LED arrays with 50-, 30-, and 10-µm pixel sizes were manufactured and characterized. The results indicated that after 4 h of air annealing and with a 3.5-μm SiO2 protective layer, the 10-µm pixel array exhibited leakage currents density 1.2 × 10−6 A/cm2 at −10 V voltage and a peak on-wafer external quantum efficiency of ~6.48%. This work suggests that the STO method could become an effective approach for future micro-LED manufacturing to mitigate adverse LED efficiency size effects due to the plasma etching and improve device efficiency. Micro-LEDs fabricated through the STO method can be applied to micro-displays, visible light communication, and optical interconnect-based memories. Almost planar pixel geometry will provide more possibilities for the monolithic integration of driving circuits with micro-LEDs. Moreover, the STO method is not limited to micro-LED fabrication and can be extended to design other III-nitride devices, such as photodetectors, laser diodes, high-electron-mobility transistors, and Schottky barrier diodes.

Impacts of diffusive ion migration on ferroelectric properties in BaTiO3 composite

Multiferroic composites, combining ferroelectric and ferromagnetic properties, hold significant promise in today’s technology landscape in a diverse array of fields including information storage devices, energy harvesters, current and magnetic field sensors, tunable devices, and various other domains. Exploring the interaction between these materials and their impact on multiferroic properties is crucial for advancing miniaturized, high-performance devices. A deeper understanding of the interplay between ionic dynamics and microstructure is essential for engineering these composites effectively. This study examines the deterioration of the ferroelectric property of BaTiO3 composite with the incorporation of the magnetic BaFe12O19. The composite is synthesized using the conventional solid-state reaction method. Structural analysis involves x-ray diffraction, Raman spectroscopy, and field-emission scanning electron microscopy. The dielectric and ferroelectric investigations, as well as magnetic analysis, are conducted. The study shows the existence of the electron hopping between different oxidation states of the cations and it elevates the material’s conductivity and, generates a leakage current that largely affects the ferroelectric properties by preventing saturation polarization.

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.