Leakage Current Reduction Research Articles

Bit swapping linear feedback shift register for low power application using 130nm complementary metal oxide semiconductor technology

Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance. In this paper, an enhanced BS-LFSR for low power application is proposed. To achieve low power dissipation, the proposed BS-LFSR introduced the stacking technique to reduce leakage current. In addition, three different architectures to enhance the feedback element used in BS-LFSR was explored. The pass transistor merged with transistor stack method yielded a better reduction in power dissipation compared to pass transistor design and NAND gate design. The BS-LFSR was designed in Mentor Graphic – TSMC Design Kit Environment using 130nm complementary metal oxide semiconductor (CMOS) technology. The proposed 4-bit BS-LFSR achieved an active area of 1241.1588um2 and consumed only 53.8844nW with total power savings of 19.43%. The proposed design showed superiority when compared with the conventional LFSR and related work in reducing power dissipation and area.

Effect of various Fe-doped AlGaN buffer layer of AlGaN/GaN HEMTs on Si substrate

AlGaN/GaN high-electron mobility transistors (HEMTs) with different Fe-doped Al0.25Ga0.75N buffer layers were fabricated on silicon (Si) substrate to improve breakdown voltage and reduce leakage current. Fe doping concentrations for the AlGaN buffer layers were designed as 5 × 1017, 6 × 1017, 7 × 1017, and 8 × 1017 cm−3. The fabricated HEMT with the Fe-doped concentration of 8 × 1017 cm−3 achieved a lower gate leakage current of 8.22 × 10−6 mA/mm, higher breakdown voltage (VBR) of −193 V, and higher buffer breakdown voltage (VBR_buffer) of −1324 V than did other devices with different doping concentrations. In addition, a slight decline in drain current dispersion in pulsed measurements and a slight increase in noise were obtained for HEMTs with a more Fe-doped buffer layer, because the increased Fe-doped concentration resulted in the formation of more buffer traps. However, these results suggest that the HEMT with a highly resistant AlGaN buffer layer of doped Fe has great potential for high-power integrated circuit applications.

Polyethylenimine Insulativity-Dominant Charge-Injection Balance for Highly Efficient Inverted Quantum Dot Light-Emitting Diodes.

Quantum dot (QD) light-emitting diodes (QLEDs) with an inverted architecture suffer from charge-injection imbalance and severe QD charging, which degrade device performance. Blocking excess electron injection into QDs is crucial for efficient inverted QLEDs. It is observed that polyethylenimine (PEI) has two opposite effects on electron injection: one is blocking electron injection by its intrinsic insulativity and the other one is promoting electron injection by reducing the work function of ZnO/PEI. In this work, the insulating nature of PEI has been dominantly utilized to reduce electron injection and the charge-injection balance is realized when PEI becomes thicker and blocks more excess electrons. Furthermore, PEI contributes to QD charging suppression and results in a smoother surface morphology than that of ZnO nanoparticles, which is beneficial for leakage current reduction and QD deposition. As a result, the optimized QLED with 15 nm PEI shows a 2.5 times improved efficiency compared to that of the QLED without PEI. Also, the QLED possesses the maximum external quantum efficiency and current efficiency of 16.5% and 18.8 cd/A, respectively, accompanied with a low efficiency roll-off of 15% at 1000 cd/m2, which is comparable to that of the reported inverted red QLED with the highest efficiency.

Three-Phase CH7 Inverter With a New Space Vector Modulation to Reduce Leakage Current for Transformerless Photovoltaic Systems

Leakage current reduction is crucial for the transformerless photovoltaic inverters. The conventional three-phase current source H6 inverter suffers from the large leakage current, which restricts its application to transformerless PV systems. In order to overcome the limitations, a new three-phase current source H7 (CH7) inverter is proposed in this paper. Only one additional Insulated Gate Bipolar Transistor is needed, but the leakage current can be effectively suppressed with a new space vector modulation (SVM). Finally, the experimental tests are carried out on the proposed CH7 inverter, and the experimental results verify the effectiveness of the proposed topology and SVM method.

EMI and ground leakage current reduction in single‐phase grid‐connected power converter

Ground leakage current in a power converter is a major concern, which has stringent limitations due to safety concerns. Presence of high-frequency pulses, with high d v /d t due to switching actions in common-mode (CM) voltage, result in injection of current waveforms with large d i /d t spikes into the ground and causes high electromagnetic interference (EMI) noise level. In this study, a new method is proposed to make the CM voltage, of a single-phase grid-connected inverter, sinusoidal and free of high-frequency pulses. The proposed method consists of two parallel connected H-bridge power converters, which uses unipolar pulse width modulation (PWM) with carrier interleaving angle of 180°. The proposed method reduces the ground leakage current by more than an order of magnitude. A novel modification to the LCL filter is proposed which further reduces the leakage current by 48%. It is shown that these modifications make the overall system insensitive to circuit non-idealities. Experimental results based on ground leakage current measurements on a 7.5 kW parallel single-phase PWM rectifier are presented. These results validate the effectiveness of the proposed method.

Enhanced magnetization and reduced leakage current by Zr substitution in multiferroic ScMnO3

Despite numerous attempts of electron doping in different manganites (RMnO3, R=rare earth), successful reports are scarce in the literature till date. In this paper, we have synthesized a series of phase-pure electron doped multiferroic compound Sc1−xZrxMnO3 (x=0, 0.05, 0.1, and 0.2) and evaluated the effect of doping on structural properties, oxidation states of cations, DC magnetization, heat capacity, resistivity, dielectric behaviour and ferroelectricity in the material. The presence of Zr4+ and mixed valence state of Mn comprising of Mn2+ and Mn3+ ions are confirmed using X-ray photoelectron spectroscopy. All these samples exhibit antiferromagnetic ordering; as Zr4+ content increases, antiferromagnetic ordering gradually diminishes while shifting to low temperatures. Additionally, ferromagnetic-like interaction develops in doped systems which gives rise to hysteresis in isothermal magnetization loops with greatly enhanced magnetization in comparison to pure antiferromagnetic nature of x=0 i.e. ScMnO3. Interestingly, even with zero magnetic moment of Sc3+, Schottky-like anomaly is observed at 5K in heat capacity data of samples with x=0.1 and 0.2, a result that we attribute to the highly resistive nature of doped samples. Moreover, while measuring ferroelectric hysteresis loops, we observe a significant reduction of leakage current in doped sample (x=0.2) compared to pure ScMnO3. Additionally, the compound x=0.2 shows improved dielectric and ferroelectric behaviour. It is proposed that doping of Zr4+ compensates for the cation deficiency and consequently eliminates the inherent oxygen vacancies by charge compensation.

Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

The use of co-sputtered Zirconium Silicon Oxide (ZrxSi1−xO2) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO2 and ZrO2 targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the ZrxSi1−xO2 film up to 600°C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr0.85Si0.15O2 dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81mV/dec), field-effect mobility (μFE=51.7cm2/Vs), and threshold voltage shift (ΔVTH=0.03V).

Salicide-Like Process for the Formation of Gate and Source Contacts in 4H-SiC TSI-VJFETs

The self-aligned approach allowed to fabricate 4H-SiC VJFETs with conventional contact lithography with only 4 lithography steps. The main problem of this approach was the gate-source leakage current. In order to address this issue, a salicide process has been adopted resulting in a substantial reduction of the gate-source leakage current. The success of this approach paved the way for fabricating high power 4H-SiC devices with extremely low fabrication cost.

Improved leakage current and device uniformity for sub-20 nm N-FinFETs by cryogenic Ge pre-amorphization implant in contact

Prior to contact silicide formation, cryogenic Ge pre-amorphization implantation (PAI) was adopted in sub-20nm FinFETs to investigate how device characteristics can be affected. As compared to room-temperature PAI, cryogenic PAI does not enhance drive current from the viewpoint of mean value, however, it significantly improves variation in device parameters such as sub-Vt swing (SS), drain induced barrier lowering (DIBL) and total series resistance (RTotal) for N-FinFETs by 22%–34% which is due to a reduced number of end of range (EOR) defects caused by Ge PAI. However, the benefit is not observed for P-FinFETs since its source/drain is composed of SiGe which is intrinsically less prone to form EOR defects. In addition, cryogenic PAI also contributes to leakage current reduction for N-FinFETs including gate induced drain leakage (GIDL) by 67%, sub-Vt leakage by 50% and junction leakage by 67% which is primarily due to a lower number of EOR defects that make fewer native point defects. The mechanism for pronounced GIDL reduction for I/O devices than core devices is also proposed. Besides the improved device uniformity as well as leakage current, the process can be fully integrated into incumbent VLSI technology and holds great potential for sub-10nm node.

Effect of Y and Mn doping into rutile type TiO2/Ge stack structure by combinatorial synthesis

The effects of Y and Mn doping into the rutile TiO2 films on a (100) Ge substrate stack structure were investigated by combinatorial synthesis. Composition spread films were fabricated by combinatorial pulsed laser deposition. Regardless of the dopant concentration, the Mn-doped TiO2 film indicated an amorphous structure. In contrast, the Y-doped TiO2 film had a rutile-type crystal structure below an Y concentration of 11.0 at. %. The high Y concentration enhanced the amorphous structure and Ge diffusion into the TiO2 layer. Although both dopants reduced leakage currents, the effect of Y was greater than that of Mn. The post-deposition annealed Y-doped TiO2 indicated an improvement in the leakage current by three orders of magnitude and electron accumulation at a capacitor structure. The Y doping into TiO2 may provide beneficial effects of good interface control and effective dielectric material for Ge-based capacitors.

Comparative analysis of single phase transformerless inverter topologies for grid connected PV system

Many single phase transformerless inverter topologies with reduced leakage current have been introduced for grid tied photovoltaic (PV) applications in the past few years. These topologies are mainly classified on the basis of leakage current reduction methods: galvanic isolation with common mode voltage (CMV) clamping and without CMV clamping. The galvanic isolation can be achieved by incorporation of extra switches either on ac side or dc side of full bridge (H4) inverter topology for ac or dc decoupling respectively. Ac side decoupling offers high efficiency due to lower number of switches in conduction path. However, it has been shown that merely by galvanic isolation, leakage current cannot be reduced to zero, because of stray junction capacitances and resonant circuit effects. Some topologies utilize CMV clamping methods to fix the CMV to half of the dc bus voltage to completely eliminate the leakage current. In this paper, several recently published topologies are reviewed, analyzed and compared. The operation principles of the topologies are discussed with their switching waveforms. The performances of the topologies are compared on the basis of CMV, leakage current, semiconductor device losses, efficiency and total harmonic distortion (THD). A modified CMV clamped H6-IV topology is also proposed to improve common mode characteristics. The analyses are carried out using Matlab/Simulink simulation, and results are verified experimentally.

Analysis and control of improved power quality single‐phase split voltage cascaded converter feeding three‐phase OEIM drive

The use of single phase induction motor (IM) in fuel dispensing units despite its poor efficiency and torque oscillations causing erroneous dispensing etc. is overdue for replacement with 3 phase IM, drives based on single phase AC-DC-AC conversion. But conventional 3 phase IM drive requires high Voltage DC tank capacitor requiring regular replacement due to short life cycle and failure on account of high induced voltage during sudden supply or loads disconnection. This paper presents a new cascaded converter active rectifier (CCAR) unit for splitting single phase to 3 phase to cater variable speed constant v/f controlled open end winding induction motor (OEIM) fuel pump drive. The proposed configuration has an advantage in terms of reduced voltage stress across each split capacitor, reduced leakage current, and distributed voltage stress during sudden supply or load disconnection. A detailed stability analysis is presented in the d - q frame for the control design to access the feasibility of drive operation. The embedded control forces balanced drive operation amidst uneven losses across the H-bridges and /or unbalanced motor loading effect during transients or intermittent operation. The effectiveness of proposed control algorithm is validated both by simulation and experimentation on the developed same scale hardware prototype.

Al2O3/AlGaN Channel Normally-Off MOSFET on Silicon With High Breakdown Voltage

A normally-Off metal-oxide-semiconductor field-effect transistor (MOS-FET) is proposed by using AlInN/AlGaN heterostructure grown on silicon. The AlGaN channel MOSFET with Al2O3 layer as gate insulator exhibits a drain current of 90 mA/mm at the gate bias of +8 V, an ON/OFF drain-current ratio of ${1.4} \times {10}^{8}$ , a peak field-effect mobility of 97 cm2/ $\text {V} \cdot \text {s}$ , and threshold voltage of +2.4 V, respectively. With significant reduction in leakage currents, the MOS-FET with a gate-to-drain spacing of 20 $\mu \text{m}$ delivers a high breakdown of 993 V. The present results of Al2O3/AlGaN normally-Off MOSFET signifies promising prospects for future high power and high voltage applications.

Design and Realization of GaN Trench Junction-Barrier-Schottky-Diodes

We present the design principle and experimental demonstrations of GaN trench junction-barrier-Schottky-diodes(trench JBSDs), where the Schottky contact within the patterned trenches is at the same plane as the adjacent p-n junctions. Assisted by the TCAD simulations, the leakage current reduction mechanism is identified as the reduced surface field (RESURF) effect due to the barrier-height difference between the p-n junction and Schottky junction. Design space for the width of stripe-shaped trenches is found to be $ for a drift layer doping level of $10^{15} \sim 10^{16}$ cm $^{-3}$ , while for circular trenches, the size requirement is relaxed. In the fabricated devices with 1– $4~\mu \text{m}$ diameter circular trenches, about 20 times reduction in the reverse leakage is observed with a characteristic shift in the turn-on voltage, which are signatures of the trench JBSD with desired RESURF. The experimental observations are in excellent agreement with the simulation results. This JBSD design shows promising potential in further improving the performance of Schottky-based GaN power devices without the need for ion-implantation or material regrowth.

Enhanced dielectric properties and energy discharge efficiency of dopamine modified (In0.05Nb0.05)Ti0.9O2 in poly(vinylidene-fluoride) composites

Dopamine@(In0.05Nb0.05)Ti0.9O2/poly(vinylidene-fluoride) (DA@INTO/PVDF) composites are fabricated via a physical mixing method followed by heat treatment. TEM results show that DA is uniformly coated on the surface of INTO particles with a thickness of 10nm. SEM results show that the DA@INTO particles are homogeneously dispersed in PVDF. Compared with INTO/PVDF composites, DA@INTO/PVDF composites exhibit excellent dielectric constant and energy discharge efficiency, which is due to the improved interfacial polarization and reduced leakage current. DA plays an important role in the enhanced dielectric properties of DA@INTO/PVDF composites.

Suppression of gate leakage current in in-situ grown AlN/InAlN/AlN/GaN heterostructures based on the control of internal polarization fields

This paper investigates the gate leakage characteristics of in-situ AlN capped InAlN/AlN/GaN heterostructures grown by metal-organic vapor phase epitaxy. It was revealed that the leakage characteristics of AlN capped InAlN/AlN/GaN heterostructures are strongly dependent on the growth temperature of the AlN cap. For an AlN capped structure with an AlN growth temperature of 740 °C, the leakage current even increased although there exists a large bandgap material on InAlN/AlN/GaN heterostructures. On the other hand, a large reduction of the gate leakage current by 4–5 orders of magnitudes was achieved with a very low AlN growth temperature of 430 °C. X-ray diffraction analysis of the AlN cap grown at 740 °C indicated that the AlN layer is tensile-strained. In contrast to this result, the amorphous structure was confirmed for the AlN cap grown at 430 °C by transmission electron microscopy. Furthermore, theoretical analysis based on one-dimensional band simulation was carried out, and the large increase in two-dimensional electron gas (2DEG) observed in Hall measurements was well reproduced by taking into account the spontaneous and piezo-electric polarization in the AlN layer grown at 740 °C. For the AlN capped structure grown at 430 °C, it is believed that the reduced polarization field in the AlN cap suppressed the penetration of 2DEG into the InAlN barrier layer, resulting in a small impact on 2DEG mobility and density. We believe that an in-situ grown AlN cap with a very low growth temperature of 430 °C is a promising candidate for high-frequency/high-power GaN-based devices with low gate leakage current.

Study of GaN-Based LEDs With Hybrid SiO2 Microsphere/Nanosphere AntiReflection Coating as a Passivation Layer by a Rapid Convection Deposition

A hybrid SiO2 micro/nanospheres antireflection coating, deposited by a rapid convection deposition, acting as a passivation layer of GaN-based light-emitting diodes (LEDs) is studied in this paper. Since the critical angle could be enlarged by antireflection coating, Fresnel reflection could be reduced. In addition, due to the roughened surface of hybrid SiO2 microsphere/nanosphere antireflection coating, the scattering effect could be increased. Thus, the light extraction efficiency could be further enhanced. As compared with a conventional LED (device A), at 20 mA, the studied device C exhibits 18.7% enhancement in light output power without any degradation of electrical properties. Reduced leakage current could also be achieved. Therefore, the use of hybrid SiO2 microsphere/nanosphere antireflection coating could effectively improve the performance of GaN-based LEDs.

Aging Benefits in Nanometer CMOS Designs

In this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.

Subthreshold FinFET SRAM at 20nm Technology with Improved Stability and Lower Leakage Power

Background/Objectives: The Complementary Metal–Oxide–Semiconductor (CMOS) scaling feature was the wonderful feature which led the electronics market into in an era of miniaturization but with the fascinating feature some limitations has also been observed. Methods/Statistical analysis: CMOS technology has also given a new horizon to the memory circuits like Static Random-Access Memory (SRAMs). To overcome the limitations of scaling of the CMOS technology, Fin Field Effect Transistor (FinFET) technology has been chosen. To overcome the limitations of scaling of the CMOS technology, FinFET technology has been chosen. Like CMOS SRAMs, FinFET SRAMs have also gained popularity because of the advantages as discussed in this paper. Findings: In this paper, FinFET SRAM cells have been proposed in three different configurations for better stability and reduced leakage power in sub threshold region at 20nm technology.4 different modes of FinFET has been used to implement the SRAM. The FinFETs are classified as (i) SG-mode (ii) LP-mode and (iii) IG mode. A comprehensive analysis has been made for all the 4 types of SRAM stability which includes for Read Margin, Write Margin, Hold Margin and leakage power analysis by finding the leakage current for all the proposed circuits and has compared with the previous work and it has been found that the proposed circuits serves better in terms of stability and reduced leakage current. The cell has been implemented for sub threshold voltages ranging from 0.4V to 0.1V. The maximum Write Margin at 0.4V is 196.9mV, Read Margin is 110 mV. Application/Improvements: It has been found that from the different SRAM circuits, IG-P has the maximum Write SNM, Read SNM and hold margin while LP mode has minimum leakage current, next the IG-P mode FinFET.

High temperature performance of Si:HfO2 based long channel Double Gate Ferroelectric Junctionless Transistors

In this work, we present a study that explores the suitability of Double Gate Ferroelectric Junctionless Transistor (DGFJL) incorporating Si:HfO2 for high temperature applications. At present, very few studies are focussed on Si:HfO2 to investigate its integrability in the present CMOS design space. Therefore, in the present study, using analytical modeling and TCAD simulations, it is demonstrated that Si:HfO2 based DGFJL exhibits superior performance in terms of substantial gain, reduced leakage currents, improved current drivability and high Ion/Ioff ratio at elevated temperatures as compared to the DGJL counterpart. The study, thus, highlights the fact that DGFJL is a potential candidate for device applications at high temperatures.