Increase In Leakage Current Research Articles

Study of the influence of gate etching and passivation on current dispersion, trapping and reliability in RF 0.15 μm AlGaN/GaN HEMTs

In this paper we examine the effect of passivation and gate etching processes on the current dispersion and reliability of AlGaN/GaN HEMTs for RF applications. We compared the performance of HEMTs with a standard gate etching and passivation processes (reference wafer) with the performances of HEMTs with improved etching process (etching variant wafer) and improved passivation process (passivation variant wafer). In order to study the trapping behavior, we performed dispersion measurements in off-state conditions and drain current transients (DCT) and we found that:1)The use of improved passivation process determines a decrease of current dispersion, in particular at the knee voltage, where current collapse depends on both threshold voltage and on-resistance variation,2)The trapping process linked to surface states is influenced by the gate etching and passivation processes; the use of improved passivation slows down the trapping/de-trapping kinetics, resulting in a lower impact on dynamic performance.The study of reliability is based on high-temperature reverse bias (HTRB) stresses. The gate-drain diodes are biased in the same voltage stress conditions (VGS,Stress = -7 V, VDS,Stress = 50 V) at high temperatures (175 °C) for 24 h. We demonstrated that the improved passivation limits the increase of gate leakage current during HTRB stress and prevents the belly shape effect linked to the presence of donor traps in the surface between SiN and GaN cap.We performed gate step stress increasing the negative voltage applied to the Schottky contact. The electroluminescence images performed during the stress show spots along the gate finger that are the responsible of the failure of the devices. The results presented in the paper provide information on the optimization of GaN HEMTs for RF applications.

Electric and Magnetic Properties of Bi0.80Ba0.20FeO3‐Doped Ba0.85Ca0.15Ti0.90Zr0.10O3 Ceramics Prepared via the Solid‐State Combustion Technique

Lead‐free (1−x)Ba0.85Ca0.15Ti0.90Zr0.10O3–xBi0.80Ba0.20FeO3 [(1−x)BCTZ–xBBF] ceramics, with BBF content (x) between 0 and 0.4, are prepared via the solid‐state combustion technique. The effect of BBF content on the phase formation, microstructure, and electric and magnetic properties of BCTZ is studied. From the Rietveld refinement analysis, the BCTZ ceramic shows coexisting orthorhombic and tetragonal phases, with a ratio of 35.4:64.6 and the percentage of the tetragonal phase continuously increases when x increases from 0.02 to 0.1, and becomes purely tetragonal at x ≥ 0.2. When x increases, the average grain size, density, and relative density continuously decrease while the unit cell volume enlarges. The dielectric constant at room temperature (εR) tends to decrease while the dielectric loss at room temperature (tan δR) increases with increased BBF content. For x = 0, a pure BCTZ ceramic, a well‐saturated P–E loop is observed with a polarization (Pr) and coercive field (Ec) of 8.94 μC cm−2 and 4.06 kV cm−1, respectively. The ferroelectricity drastically decreases with x = 0.02. For x ≥ 0.06, the leakage current increases, which suppresses the ferroelectricity. With no BBF content (x = 0), the ceramic has diamagnetic properties that change to paramagnetic properties with x = 0.02–0.06 and finally to ferromagnetic properties when the BBF increases between 0.10 and 0.40. For x = 0.10–0.40, the remnant magnetization (Mr) continuously increases.

Impact of Anode Doping on Avalanche in Vertical GaN Pin Diodes with Hybrid Edge Termination Design

Introduction: Large area GaN power devices are seldom reported to avalanche and the theoretical studies of their edge termination still struggle to match experimental results especially for planar structures. We report for the first time a punch through avalanche on 1.2 kV vertical GaN diode with optimized hybrid edge termination design to fit the device structure. Furthermore, we provide a systematic study that pairs the Sentaurus TCAD simulation to the reverse characteristics of three different anode designs with three different remaining dose in the anode extension region. Device Fabrication: PiN diodes with three different anode doping were fabricated on a non-homogenous GaN substrate. 5×1017, 1×1018, and 2×1019 cm-3 Mg-doped layer were grown on a MOCVD lightly doped layer of 8um with doping concentration of the order of 1-2×1016 cm-3. The Edge termination process starts with etching a trench 1µm depth and about 140µm from anode edge, followed by isolation nitrogen implant using a box profile with three different energies and total depth of ~650 nm. Finally, the junction termination extension and guard rings (JTE/GR) hybrid is implemented by nitrogen implant to achieve a full planar device structure with final depth of 300 nm. Figure 1 depicts the device structure. The same JTE/GR hybrid implant depth into three different anode doping which results in different residual charge in the extension region thickness that is expected to impact the field management. Experimental Result: Three devices with the different anode doping were tested under identical forward and reverse biases conditions. The three devices display similar forward behavior with ideality factor ranging 2<n<2.2 as shown in Figure 2. Their reverse characteristics however, are varying proportional to the anode doping. The highest breakdown voltage and the sharpest breakdown characteristics was displayed by anode doping of 1×1018 cm-3. The other two anode doping devices fail short to achieve the expected breakdown voltage and both devices also exhibit higher leakage than the 1×1018 cm-3.. All devices are designed to withhold 1.2 kV, thus 2×1019 and 5×1017 cm-3 anode are ~ 500 V away from the targeted value. Considering the fact that these three wafers have the same drift region thickness and doping, and were processed together through the edge termination therefore, the drastic difference in the breakdown voltage can be only explained by the remaining dose in the extension region. To further understand the edge termination efficacy in these devices an avalanche test was conducted, reverse sweep was applied at 25,100,150, &200 °C for all three devices. Figure 3 depicts the avalanche results. Both devices with 1×1019 and 5×1017 are struggling to avalanche due to the high leakage and inconsistent trend with temperature. The PiN diode with 1×1018 cm-3 avalanched with an increase of breakdown voltage 10 V for every 50 °C. This trend of the breakdown with temperature is possible due to the increase in leakage current, consequently a temperature coefficient α= 3.1×10-4 K-1 was calculated using equation: . To better understand this difference a simulation was conducted using Sentaurus TCAD. The model is designed to observe the behavioral trends thus the absolute numbers in the model do not capture the devices non-idealities. The 2D distribution of the electric field is displayed in Figure 4 for all 3 doing levels. Conclusion: The reverse characteristic and TCAD simulation indicate an improvement in the field management with the decrease in the anode doping to 1×1018 cm-3 which subsequently means less charges in the edge termination region than the standard 2×1019 doping level . These results show that the anode dose is a function of anode doping level, implant depth and the edge termination region thickness. To optimize edge termination design one needs to manage the dose in the termination region which is a function of anode doping level, implant depth and the edge termination region thickness. Figure 1

Using Data Science and Machine Learning to Predict the Failure Rate of Pin Diodes

GaN research is important to the development of next generation power conversion technology because its large Baliga figure of merit GaN gives it the potential to outperform SiC. Presently, commercialized GaN technology is based on lateral high electron mobility transistors (HEMTs); however, large areas would be required for high voltage applications thus there is motive to switch to vertical GaN. Current GaN substrate manufacturing technology is known to produce inconsistent quality with a varying concentration of defects. These defects are known to cause catastrophic device failure, thus there is motive to develop quick, non-destructive techniques to predict the quality of the wafer before undergoing the expensive fabrication process. This talk focuses on using data science and machine learning to predict the quality of the diodes.This work demonstrated that Raman spectroscopy can be used to detect high crystal stress points, which strongly correlates with an increased leakage current. Optical profilometry images can be used to detect defects that cause catastrophic failures; however, the presence of benign defects makes it difficult to predict the device quality using a simple algorithm. Thus, a machine learning algorithm relate optical profilometry images to device performance of subsequently processed device. The results showed that this algorithm was 91% accurate at predicting the forward bias behavior of devices, and it is possible that the devices it could accurately predict failures due to device processing errors.This work was supported by the Office of Naval Research.

(Dielectric Science & Technology Thomas Callinan Award) Materials and Processes As Enablers for Moore Moore and Beyond Moore Technologies

In this presentation, an overview will be presented of historic and recent developments achieved w.r.t. materials and processes that enabled continued performance scaling of CMOS and beyond CMOS applications. Starting from early high-k work. For decades, thermal oxidation of crystalline Silicon into SiO2 has been the gate oxide material in CMOS technology. Miniaturization for performance improvement, required the gate dielectric to decrease in thickness to support the required increase in capacitance (per unit area) and drive current (per device width). Early 2000, the thickness scaled below 1.5 nm, causing drastically increased leakage currents, high power consumption and reduced device reliability. Replacing the SiO2 gate dielectric with a high-κ (dielectric constant) material allows increased gate capacitance without the associated leakage effects. Activities involved the unit process step development of dielectric and metal deposition processes, advanced interface preparation, electrical and physical characterization and wet and dry etch process development. In a second section, emphasis will be on emerging nanomaterials. Nanotechnology is defined as the manipulation of matter with at least one dimension sized from below 100nm, thus all CMOS activities are functional nanotechnology. The latter concentrated initially on Graphene, but extended further towards Transition Metal Dicalchogenide Materials. Emphasis of the work will be on growth, functionalization, dielectric passivation and doping of these materials. Lastly, expanding on the nanomaterial know-how also progress with regard to low-k dielectrics, area selective deposition processes (for bottom-up lithography) and application of nanochemistry research for photoresist material screening, where chemical interactions at the nanoscale, related to the EUV lithography (radiation chemistry) are hampering the pattern scaling.Throughout the presentation, recognition will be given to people (PhD students) that contributed to this work and the presentation is also in honor of Prof Dolf Landheer and Professor Samares Kar with whom I organized my first ECS symposium.

Research on the Synergistic Effect of Total Ionization and Displacement Dose in GaN HEMT Using Neutron and Gamma-Ray Irradiation.

This paper studies the synergistic effect of total ionizing dose (TID) and displacement damage dose (DDD) in enhancement-mode GaN high electron mobility transistor (HEMT) based on the p-GaN gate and cascode structure using neutron and 60Co gamma-ray irradiation. The results show that when the accumulated gamma-ray doses are up to 800k rad(Si), the leakage-current degradations of the two types of GaN HEMTs with 14 MeV neutron irradiation of 1.3 × 1012 n/cm2 and 3 × 1012 n/cm2 exhibit a lower degradation than the sum of the two separated effects. However, the threshold voltage shifts of the cascode structure GaN HEMT show a higher degradation when exposed to both TID and DDD effects. Moreover, the failure mechanisms of the synergistic effect in GaN HEMT are investigated using the scanning electron microscopy technique. It is shown that for the p-GaNHEMT, the increase in channel resistance and the degradation of two-dimensional electron gas mobility caused by neutron irradiation suppresses the increase in the TID leakage current. For the cascode structure HEMT, the neutron radiation-generated defects in the oxide layer of the metal–oxide–semiconductor field-effect transistor might capture holes induced by gamma-ray irradiation, resulting in a further increase in the number of trapped charges in the oxide layer.

Evaluation of structural, morphological, optical, and electrical properties of zinc oxide semiconductor nanoparticles with microwave plasma treatment for electronic device applications

ZnO is an important II-IV n-type direct bandgap semiconductor material that has exhibited wide consideration due to its applications in optoelectronic devices. In the present investigation, untreated and plasma-treated ZnO NPs were fabricated by a sol-gel route and analyzed with XRD, Raman, UV-Vis spectra, and I–V characteristic techniques. To be used in electronic applications, the ZnO nanoparticles were subjected to a plasma treatment process to tune their optical, vibrational mode, structural and electrical properties. XRD confirmed the pure Wurtzite tetragonal phase crystalline nature of produced samples. The average crystalline size, lattice constant, unit cell volume, and porosity were found in the range of 3.81–4.68 nm, a = 3.217–3.323 Å and c = 2.032–2.178 Å, 5.662–11.274 Å3 and 7.09–5.03%, respectively. The Raman spectra revealed that the intensity of Raman bands was increased due to the increase in the vibrational amplitude and increase in force constants with the enhancement in grain size, these spectra results are in good agreement with XRD and reveal the purity of samples. The bandgap found reduced from 3.56 eV to 3.39 eV by plasma treatment. The electrical studies revealed that plasma treatment improves the electrical properties of ZnO NPs without producing any structural distortions. I–V characteristic curves confirmed that the conductivity was increased from 8.3 X 10−6 to 5.5 X 10−4 ℧ cm−1 on plasma treatment which caused an increase in leakage current. The improved structural, vibrational mode, optical and electrical properties of prepared ZnO NPs make them a suitable candidate for application in electronic devices.

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes.

This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.

Local strain modification effects on global properties of AlGaN/GaN high electron mobility transistors

Performance and reliability of microelectronic devices are governed by the mechanical strain within the device layers. Typically, this is studied with uniformly distributed strain applied externally or internally. The focus of this study is on AlGaN/GaN high electron mobility transistors (HEMTs), which is expected to be more sensitive to strain due to its piezo-resistive and piezo-electric nature. Accordingly, we hypothesize that even small but localized strain may have significant impact on the overall behavior of a HEMT. To investigate this hypothesis, we introduce highly localized strain relief by milling a 20 × 30 μm2 micro trench about 70 μm deep on the backside of an 800 × 840 μm2 size HEMT die. The resulting local relaxation of in-plane residual strain was mapped using micro-Raman technique. Our results show that a decrease of only 0.02% strain can decrease the overall output saturation current up to ~20%. The drop of output current is attributed to reduced two-dimensional electron gas (2DEG) sheet carrier density and electron mobility due to the strain relief in the device layers. However, the mechanistic process of strain relief also causes defect generation at the interfaces, which increases leakage current. Our technique for localized strain re-distribution could be an effective tool to surrogate the influence of inherent localized strain build-up across the channel of electronic devices.

Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate (PG) transistors on write margin considering the negative BL (NBL) assist technique.

Degradation Characteristics and Reliability Assessment of 1310 nm VCSEL for Microwave Photonic Link

The long-term reliability of the commercially available vertical-cavity surface-emitting laser (VCSEL) at 1310 nm wavelength is investigated. To do so, a high current accelerated life test is used to evaluate the 1310 nm VCSEL reliability. Variations of properties that depend on the operating condition are characterized by the light-current-voltage, leakage current and low-frequency noise. When the aging current is 6 mA, 8 mA and 10 mA, the maximum output power reduces by 5%, 6% and 15% of the initial value, respectively. It is demonstrated theoretically and experimentally that the leakage current increases and reverse bias breakdown voltage decreases after the accelerated current aging test. The current noise power spectral density increases after the device ages, and the noise increases with the augment of the electrical stress. When the bias current of VCSEL is below the threshold, the frequency index factor and noise amplitude gradually increase with the bias current increase. Further, lifetime fitting curves of the devices at an accelerating current of 6 mA, 8 mA and 10 mA are obtained, and the median lifetime of 67 years at the operating current is extrapolated.

A SiC sidewall enhanced trench JBS diode with improved forward performance

A new high-performance sidewall enhanced trench junction barrier Schottky (SET-JBS) diode is proposed in this article. In the proposed SET-JBS diode, in addition to the Schottky contact on the top anode, the sidewall of the trenches also introduces Schottky contacts, which not only increases the Schottky contact area, but also weakens the junction field-effect transistor effect of the device, resulting in a high forward current density and a low specific on-resistance (R on,sp) with a small increase in reverse leakage current (J L). Simulation results show that the R on,sp of the proposed SET-JBS diode is reduced by 21.6%–46.7% with less than an order of magnitude increase in leakage current compared with that of the conventional trench JBS (T-JBS) diode when the trench distance is from 2.1 μm to 1.2 μm at the 2 μm trench depth. And the SET-JBS diode also performs better than the trench MOS barrier Schottky (TMBS) diode when comprehensively considered the R on,sp and J L. And the figure of merit and the trade-off relationship between the R on,sp and the breakdown voltage of the proposed SET-JBS both are better than those of the conventional T-JBS diode and TMBS diode. The forward I–V analytical model of the SET-JBS is also proposed, which is in good agreement with the simulation results. All the simulation results indicate that the proposed SET-JBS diode has promising potential in power electronics applications.

SUNSTORM 1/X-ray Flux Monitor for CubeSats (XFM-CS): Instrument characterization and first results

SUNSTORM 1 CubeSat was launched to Sun-synchronous low Earth orbit on August 17 2021. The primary purpose of the mission is an in-orbit demonstration of X-ray Flux Monitor (XFM) instrument. XFM is an innovative solar X-ray spectrometer for measuring and characterizing solar flares, which are known to be linked to a variety of space weather phenomena. XFM represents a next generation of solar X-ray flux monitors. It is based on silicon drift detector technology, which provides several notable performance improvements over its predecessors, which are based on Si PIN detectors. Transversal electric field and lower output capacitance allow operation at much faster pulse processing shaping times, allowing the system to achieve about 10 times higher throughput without saturation while also making it less sensitive to the increase of leakage current due to high temperature and/or radiation damage. Thus, XFM instruments can cover a very wide dynamic range of solar X-ray emission from the most quiescent conditions to the strongest X-class solar flares, while maintaining good spectral resolution (<200 eV at 6 keV). The instruments are thus well suited for both X-ray flux monitoring and spectroscopic studies of the solar corona.In this paper we describe the ground characterization and evaluation of the scientific performance of the first operational XFM instrument, a CubeSat version XFM-CS on-board SUNSTORM 1, which is a satellite built in the framework of the FLY element of ESA’s General Support Technology Programme, dedicated to the early space testing of promising new technologies. We also provide an analysis of the first results obtained during the in-orbit commissioning and early operations of SUNSTORM 1. We show the comparison of the observed scientific performance of XFM-CS with the expected performance based on theoretical modeling and ground calibration results. Finally, we describe the cross calibration of the X-ray flux data from XFM-CS with the new GOES-R series GOES X-ray sensors.

Thermo-mechanical aspects of gamma irradiation effects on GaN HEMTs

We report thermal and mechanical responses accompanying electrical characteristics of depletion mode GaN high electron mobility transistors exposed to gamma radiation up to 107 rads. Changes in the lattice strain and temperature were simultaneously characterized by changes in the phonon frequency of E2 (high) and A1 (LO) from the on-state and unpowered/pinched off reference states. Lower doses of radiation improved electrical properties; however, degradation initiated at about 106 rads. We observed about 16% decrease in the saturation current and 6% decrease in the transconductance at the highest dose. However, a leakage current increase by three orders of magnitude was the most notable radiation effect. We observed temperature increase by 40% and mechanical stress increase by a factor of three at a dose of 107 rads compared to the pristine devices. Spatial mapping of mechanical stress along the channel identifies the gate region as a mechanically affected area, whereas the thermal degradation was mostly uniform. Transmission electron microscopy showed contrast changes reflecting a high vacancy concentration in the gate region. These findings suggest that localized stress (mechanical hotspots) may increase vulnerability to radiation damage by accommodating higher concentration of defects that promote the leakage current.

Study of Electrical Performance of Hetero-Dielectric Gate Tunnel Field Effect Transistor (HDG TFET): A Novel Structure for Future Nanotechnology

Although, dynamic power in portable mobile devices can be reduced by reducing power supply VDD on the cost of increased leakage current. Therefore, maintaining low leakage current in the device is serious issue for minimizing overall power consumption of the circuit and improving the battery life. The conventional Metal Oxide Field Effect Transistor (MOSFET) requires at least 60 mV of gate voltage for better current drive at room temperature which is difficult to achieve due to thermal limit. This limitation of gate voltage requirement degrades the performance of the device at lower VDD. Tunnel Field Effect Transistor (TFET) is a potential candidate to replace CMOS in deep-submicron region due to its lower subthreshold slope SS (&lt; 60 mV/decade) at room temperature. Steep switching in TFET can extend the supply voltage scaling with improved energy efficiency for both digital and analog applications. Despite those advantages, TFETs are suffering from lower ON current and larger ambipolar current. To overcome these shortcomings, a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Since, in the absence of the compact analytical model, it is difficult to understand the electrical behaviour of the HDG TFET device, therefore, the present paper presents an analytical model of transconductance parameter of HDG TFET device. The electrical performance analysis of HDG TFET device reflects that on current can be increased considerably by choosing gate material of higher work function near the source region which also suppresses the ambipolar current. It is also observed that a thinner silicon film and larger drain bias result in larger transconductance value.

Comparison of artificial intelligence techniques to failure prediction in contaminated insulators based on leakage current

Contamination in insulators results in an increase in surface conductivity. With higher surface conductivity, insulators are more vulnerable to discharges that can damage them, thus reducing the reliability of the electrical system. One of the indications that the insulator is losing its insulating properties is its increase in leakage current. By varying the leakage current over time, it is possible to determine whether the insulator will develop an irreversible failure. In this way, by predicting the increase in leakage current, it is possible to carry out maintenance to avoid system failures. For forecasting time series, there are many models that have been studied and the definition of which model is suitable for evaluation depends on the characteristics of the data associated with the analysis. Thus, this work aims to identify the most suitable model to predict the increase in leakage current in relation to the time the insulator is outdoors, exposed to environmental variations using the same database to compare the methods. In this paper, the models based on linear regression, support vector regression (SVR), multilayer Perceptron (MLP), deep neural network (DNN), and recurrent neural network (RNN) will be analyzed comparatively. The best accuracy results for prediction were found using the RNN models, resulting in an accuracy of up to 97.25%.

Effect of Isothermal Conditions on the Charge Trapping/Detrapping Parameters in e-Beam Irradiated Thermally Aged XLPE Insulation in SEM.

The effect of isothermal conditions on the trapping/detrapping process of charges in e-beam irradiated thermally aged XLPE insulation in scanning electron microscopy (SEM) has been investigated. Different isothermal conditions ranging from room temperature to 120 °C are applied on both unaged and aged XLPE samples (2 mm thick) by a suitable arrangement associated with SEM. For each applied test temperature, leakage, and influence currents have been measured simultaneously during and after e-beam irradiation. Experimental results show a big difference between the fresh and aged material regarding trapping and detrapping behavior. It has been pointed out that in the unaged material deep traps govern the process, whereas the shallow traps take part in the aged one. Almost all obtained results reveal that the trapped charge decreases and then increases as the temperature increases for the unaged sample. A deflection temperature corresponding to a minimum is observed at 50 °C. However, for the aged material, the maximum trapped charge decreases continuously with increasing temperature, and the material seems to trap fewer charges under e-beam irradiation at high temperature. Furthermore, thermal aging leads to the occurrence of detrapping process at high temperatures even under e-beam irradiation, which explains the decrease with time evolution of trapped charge during this period. The recorded leakage current increases with increasing temperature for both cases with pronounced values for aged material. The effect of temperature and thermal aging on electrostatic influence factor (K) and total secondary electron emission yield (σ) were also studied.

Effect of Frequency on Total Ionizing Dose Response of Ring Oscillator Circuits at the 7-nm Bulk FinFET Node

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized under dynamic and static test conditions through changes in ring oscillator (RO) frequencies, leakage currents, and inverter delays. Results from total-dose exposures using the ARACOR X-ray machine showed that static conditions represented the worst case conditions. Higher operating frequencies resulted in increased leakage currents and inverter delays after irradiation. The rate of change for leakage current was inversely proportional to frequency during exposure. The rate of change for inverter delay was directly related to frequency during TID exposure. Overall, degradations in circuit-level parameters (logic gate delays and operating current) were less than 1% for TID exposures of 435 krad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ).

Reducing the Effect of Carry Propagation on Spintronic Adders

Due to the exponential increase of transistor leakage currents, especially in the technologies lower than 90[Formula: see text]nm, the static power consumption has dramatically increased. So, it is regarded as one of the main problems of the CMOS circuits. The spintronic devices, such as magnetic tunnel junction (MTJ), have notable advantages including low-static power consumption, nonvolatility, high endurance, compatibility with the CMOS transistors and the possibility of fabrication in high scales. Hence, the hybrid MTJ/CMOS circuits are considerable options to mitigate the problem of high-static power consumption in CMOS circuits. In this paper, a nonvolatile and low-power hybrid MTJ/CMOS full adder is proposed for implementation of in-memory computing. The drawback of existing full adders is their low-speed and high-power consuming for MTJ switching, which terribly affect the performance of multi-bit adders using these full adders. In this work, a new full adder is designed by eliminating the MTJ and transistor related to the input carry bit and modifying the tree structure of the MTJ network associated with the other inputs. In the proposed full adder, the effect of carry propagation has drastically decreased and its power consumption is also improved.

Improved Power Performance and the Mechanism of AlGaN/GaN HEMTs Using Si-Rich SiN/Si3N4 Bilayer Passivation

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Si-rich SiN/Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> bilayer passivation were studied in this article. The use of a Si-rich SiN interlayer leads to improved channel transport property, current collapse, power performance, and temperature-dependent stability. Devices without Si-rich SiN interlayer passivation exhibit an increase in the gate leakage current by over three orders of magnitudes with temperature increasing from 300 to 420 K, leading to an increase in a current collapse from 9.7% to 24.7%, while the devices with Si-rich SiN passivation exhibit a weak temperature dependence of leakage current and a constant current collapse about 5%. Small signal characterization shows that Si-rich SiN passivation results in a remarkable decrease in the effective gate length by ~15% with temperature up to 420 K. At 17 GHz, devices with Si-rich SiN interlayer passivation exhibit an output power density of 7 W/mm and a peak power-added efficiency (PAE) of 56%. The improved power performance of devices using Si-rich SiN interlayer passivation is attributed to the suppressed current collapse and superior device stability under high channel temperature.