Leakage Current Degradation Research Articles

Ultralow-Capacitance Through-Silicon Vias With Annular Air-Gap Insulation Layers

Low capacitance is critical to the electric performance of through-silicon vias (TSVs). This paper reports the development and electrical characterization of ultralow-capacitance TSVs which use air gaps to replace the conventional silicon dioxide as the insulation layers. The air-gap TSVs are successfully fabricated by developing a sacrificial technology which uses void-free filling and selective etching of an annular benzocyclobutene polymer cladding that surrounds copper plugs. The capacitance and the leakage current are tested to characterize the electrical performance. The lowest effective dielectric constant of the air enables the capacitance of the air-gap TSVs to be as low as 24 fF, and the capacitance density is more than one order of magnitude lower than that of conventional SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> liner TSVs. The leakage current to the substrate is 3 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> A at 40 V, and no leakage current degradation occurs after a 40-cycle thermal shock test. The preliminary results demonstrate the new air-gap structure and the efficacy of air gaps in reducing TSV capacitance.

Transferred wrinkled Al2O3 for highly stretchable and transparent graphene–carbon nanotube transistors

Despite recent progress in producing transparent and bendable thin-film transistors using graphene and carbon nanotubes, the development of stretchable devices remains limited either by fragile inorganic oxides or polymer dielectrics with high leakage current. Here we report the fabrication of highly stretchable and transparent field-effect transistors combining graphene/single-walled carbon nanotube (SWCNT) electrodes and a SWCNT-network channel with a geometrically wrinkled inorganic dielectric layer. The wrinkled Al2O3 layer contained effective built-in air gaps with a small gate leakage current of 10(-13) A. The resulting devices exhibited an excellent on/off ratio of ~10(5), a high mobility of ~40 cm(2) V(-1) s(-1) and a low operating voltage of less than 1 V. Importantly, because of the wrinkled dielectric layer, the transistors retained performance under strains as high as 20% without appreciable leakage current increases or physical degradation. No significant performance loss was observed after stretching and releasing the devices for over 1,000 times. The sustainability and performance advances demonstrated here are promising for the adoption of stretchable electronics in a wide variety of future applications.

Degradation mechanism of leakage current in AlGaN/GaN high electron mobility transistors

In order to study the degradation mechanism of leakage current in AlGaN/GaN high electron mobility transistors (HEMTs), we have fabricated AlGaN/GaN heterojunction Schottky diodes having equivalent structure and characteristics to AlGaN/GaN HEMTs. Step stress tests were then performed to compare the leakage current changes at different gate voltages. The transport mechanism of leakage current before and after degradation was validated based on the current-voltage and capacitance-voltage measurements. The light emission from the device surface was examined by emission microscopy (EMMI) to investigate the time-dependent degradation of leakage current. Experimental results show that the leakage current increases with increasing time and is accompanied by a large noise when the applied gate voltage exceeds a critical value. After introducing the polarization field into the current-field dependence, log(IFT/E) exhibits a good linear relationship with E both before and after degradation, indicating that the leakage current is dominated by the Frenkel-Poole (FP) emission. The slope of log(IFT/E)-E curve decreases after degradation, and the hot spots corresponding to defects are directly observed by EMMI at the gate edge of the degraded device, suggesting that the degradation mechanism is: New defects are induced by high electric field in the AlGaN layer, and the increase of defect density leads to the increase of FP emission current.

Accelerated Aging Effect on Epoxy-polysiloxane Polymeric Insulator Material with Rice Husk Ash Filler

The performances of outdoor polymeric insulators are influenced by environmental conditions. This paper presents the effect of artificial tropical climate on the hydrophobicity, equivalent salt deposit density (ESDD), surface leakage current, flashover voltage, and surface degradation on epoxy-polysiloxane polymeric insulator materials with rice husk ash (RHA). Test samples are made at room temperature vulcanized (RTV) of various composition of epoxy-polysiloxane with rice husk ash as filler. The aging was carried out in test chamber at temperature from 50 o C to 62 o C, relative humidity of 60% to 80%, and ultraviolet (UV) radiation 21.28 w/cm 2 in daylight conditions for 96 hours. The experiment results showed that the flashover voltage fluctuates from 34.13 kV up to 40.92 kV and tends to decrease on each variation of material composition. The surface leakage current fluctuates and tends to increase. Test samples with higher filler content result greater hydrophobicity, smaller equivalent salt deposit density, and smaller critical leakage current, which caused the increase of the flashover voltage. Insulator material (RTV EP3 )showed the best performance in tropical climate environment. Artificial tropical aging for short duration gives less effect to the surface degradation of epoxy-polysiloxane insulator material. DOI: http://dx.doi.org/10.11591/telkomnika.v10i4.846

Accelerated Aging Effect on Epoxy-polysiloxane-Rice Husk Ash Polymeric Insulator Material

The performances of outdoor polymeric insulators are influenced by environmental conditions. The use of polymeric materials in a particular composition can be produced insulators that are resistant to environmental influences. This paper presents the effect of artificial tropical climate on the hydrophobicity, equivalent salt deposit density (ESDD), surface leakage current, flashover voltage, and surface degradation on epoxy-polysiloxane polymeric insulator materials with rice husk ash (RHA). Test samples are made at room temperature vulcanized (RTV) of various composition of epoxy-polysiloxane with rice husk ash as filler. The aging was carried out in test chamber at temperature from 50oC to 62oC, relative humidity of 60% to 80%, and ultraviolet (UV) radiation 21.28 w/cm2 in daylight conditions for 96 hours. The experiment results showed that the flashover voltage fluctuates from 34.13 kV up to 40.92 kV and tends to decrease on each variation of material composition. The surface leakage current fluctuates and tends to increase. Test samples with higher filler content result greater hydrophobicity, smaller equivalent salt deposit density, and smaller critical leakage current, which caused the increase of the flashover voltage. Insulator material (RTVEP3) showed the best performance in tropical climate environment. Artificial tropical aging for short duration gives less effect to the surface degradation of epoxy-polysiloxane insulator material.

Design guideline of a thin film SOI power MOSFET for high thermal stability

This paper proposes the design guidelines of the thin-film reduced surface field (RESURF) SOI power MOSFET for high thermal stability based on experimental and simulation results. The results show that the thinner top silicon layer is preferable, which realize the lower leakage current and smaller degradation of the on-resistance. In higher temperature operation, it is important to suppress the parasitic bipolar effect to prevent the reduction of the breakdown voltage.

Accelerated Aging Effect on Epoxy-polysiloxane Polymeric Insulator Material with Rice Husk Ash Filler

The performances of outdoor polymeric insulators are influenced by environmental conditions. This paper presents the effect of artificial tropical climate on the hydrophobicity, equivalent salt deposit density (ESDD), surface leakage current, flashover voltage, and surface degradation on epoxy-polysiloxane polymeric insulator materials with rice husk ash (RHA). Test samples are made at room temperature vulcanized (RTV) of various composition of epoxy-polysiloxane with rice husk ash as filler. The aging was carried out in test chamber at temperature from 50 o C to 62 o C, relative humidity of 60% to 80%, and ultraviolet (UV) radiation 21.28 w/cm 2 in daylight conditions for 96 hours. The experiment results showed that the flashover voltage fluctuates from 34.13 kV up to 40.92 kV and tends to decrease on each variation of material composition. The surface leakage current fluctuates and tends to increase. Test samples with higher filler content result greater hydrophobicity, smaller equivalent salt deposit density, and smaller critical leakage current, which caused the increase of the flashover voltage. Insulator material (RTV EP3 )showed the best performance in tropical climate environment. Artificial tropical aging for short duration gives less effect to the surface degradation of epoxy-polysiloxane insulator material. DOI: http://dx.doi.org/10.11591/telkomnika.v10i4.846

Nanoscale SiGe-on-insulator (SGOI) MOSFET with graded doping channel for improving leakage current and hot-carrier degradation

A novel graded doping profile, for the first time is introduced for reliability improvement and leakage current reduction. The proposed structure is called graded doping channel SiGe-on-insulator (GDC-SGOI). The key idea in this work is to modify the electric field and band energy with novel doping distribution in the channel for improving leakage current and hot electron. Using two-dimensional two-carrier simulation we demonstrate that the GDC-SGOI shows lower electron temperature near the drain region in the channel in comparison with the conventional SGOI (C-SGOI) with uniform doping. On the other hand, short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement leads to leakage current reduction. DIBL decrement and less dependence of the threshold voltage and DIBL on channel length variation in the GDC-SGOI structure show SCEs suppression. Furthermore the on–off current ratio ( I on/ I off) in the GDC-SGOI is higher than that achieved from the C-SGOI. Therefore, the results show that the GDC-SGOI structure especially in low power and device reliability has excellent performance in comparison with the C-SGOI.

Comprehensive Study on the Total Dose Effects in a 180-nm CMOS Technology

The effects of total ionizing on a 180-nm CMOS technology are comprehensively studied. Firstly, we show new results on the hump effect which has strong relationship to the STI corner oxide thickness. Secondly, the leakage current degradation in various devices after radiation is investigated. For the intra-device leakage, both body doping concentration and STI corner thickness play very important roles. For the inter-device leakage, due to the low electric field at the STI bottom, it is found to be insensitive to ionizing radiation. Thirdly, a method for extracting the effective threshold voltage of the sidewall parasitic transistor is proposed by studying the leakage output characteristics. Finally, we find that the drain saturation current increases in NMOS transistors after radiation, especially in the narrow-channel ones.

Modified Percolation Model for Polycrystalline High-$ \kappa$ Gate Stack With Grain Boundary Defects

We modify the existing oxide breakdown (BD) percolation model in this letter to account for the presence of microstructural weakest link grain boundary (GB) defects in polycrystalline high-κ (HK) gate stacks. The different rates of the stress-induced leakage current degradation and oxide trap generation at the bulk and GB regions need to be accounted for in modeling the statistical nature of BD in HK dielectric thin films. Simulated results reveal the dominance of GB-related failures and the origin of the non-Weibull stochastics inherent in polycrystalline HK stacks. We also point to the inability of conventional percolation models with an assumed uniform defect generation to describe the failure statistics of current HK gate stacks.

Effective Work Function Modulation by Aluminum Ion Implantation on Hf-Based High- $k$/Metal Gate pMOSFET

The impact of aluminum (Al) implantation into TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> / SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> on the effective work function is investigated. Al implanted through poly-Si cannot attain sufficient flatband voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> ) shift unless at higher implantation energy. Al implanted through TiN at 1.2 keV with a dose of 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> raised the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> to about 250 mV compared with a nonimplanted gate stack. Moreover, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> shift can be up to about 800 mV at 2 keV with the same dose level accompanied with slightly equivalent oxide thickness penalty and gate leakage current degradation. Optimized process window to control Al diffusion depth was essential to minimize these impacts.

Electrical impact of line-edge roughness on sub-45-nm node standard cells

Since line-end roughness (LER) has been reported to be of the order of several nanometers and to not decrease as the device shrinks, it has evolved as a critical problem in sub-45-nm devices and may lead to serious device parameter fluctuations and performance limitations for future very large scale integration (VLSI) circuit applications. We present a new cell characterization methodology that uses the nonrectangular gate print images generated by lithography and etch simulations with the random LER variation. We systematically analyze the random LER by taking the impact on circuit performance due to LER variation into consideration. We observed that the saturation current, delay, and leakage current are highly affected by LER as the gate length becomes thinner. Results show that when the root mean square value of LER is 6 nm from its nominal line edge, the worst case saturation current, delay, and leakage current degradation are as much as 10.3% decrease, 12.4% increase, and 7× increase at a 45-nm-node standard cell. Meanwhile the current, delay, and leakage current degradation at a 32-nm-node cell are up to 19.0% decrease, 21.8% increase, and 4600× increase, respectively.

Leakage Current in TiN/HfO2/TiN MIM Capacitors and Degradation Due to Electrical Stress

Electrical characteristics of TiN/HfO2/TiN capacitors have been investigated by means of leakage current and Random Telegraph Noise measurements. Trap assisted transport simulation allowed the extraction of relevant parameters like trap density and trap energy position. The extracted parameters show striking similarities with those reported for HfO2 deposited on a Si surface (i.e., MOSFET applications). Additionally, even low bias Constant Voltage Stress was found to induce leakage current degradation on current vs voltage characteristics, preferentially at low voltage. The leakage current degradation is explained by preexisting defect precursors or by involvement of hydrogen in creating defects as observed on thermal SiO2 layers.

Correlation between Physical Defects and Performance in AlGaN/GaN High Electron Mobility Transistor Devices

Microstructural origins of leakage current and physical degradation during operation in product-quality AlGaN/GaN high electron mobility transistor (HEMT) devices were investigated using photon emission microscopy (PEM) and transmission electron microscopy (TEM). AlGaN/GaN HEMTs were fabricated with metal organic chemical vapor deposition on semi-insulating SiC substrates. Photon emission irregularity, which is indicative of gate leakage current, was measured by PEM. Site specific TEM analysis assisted by a focused ion beam revealed the presence of threading dislocations in the channel below the gate at the position showing strong photon emissions. Observation of electrically degraded devices after life tests revealed crack/pit shaped defects next to the drain in the top AlGaN layer. The morphology of the defects was three-dimensionally investigated via electron tomography.

Asymmetric Negative Bias Temperature Instability Degradation of Poly-Si TFTs under Static Stress

This work investigates the asymmetric negative bias temperature instability (NBTI) degradation of poly-Si thin film transistors (TFTs). Electric measurements of normal and reverse modes are employed to analyze degradation of threshold voltage, current, leakage current, and subthreshold swing. The results indicate that a nonuniform vertical electric field at the poly- interface results in an asymmetric NBTI degradation. The trap generation density gradually diminishes from source to drain. This paper also presents energy diagrams to explain the experimental data; these indicate that asymmetric TFT degradation results from the distribution of the trap state induced by an asymmetric NBTI.

Charge Trapping Related Degradation of Thin HfAlO ∕ SiO2 Gate Dielectric Stack during Constant-Voltage Stress

Charge carrier generation/trapping and the related degradation of a thin stack in n-type metal-oxide-semiconductor capacitors have been investigated under constant gate voltage stress. The results show that dielectric degradation is a composite effect of neutral trap creation, surface state generation at the interface, and positive charge trapping in the bulk. The neutral traps created during stress are homogeneously distributed across the oxide following Poisson’s random statistics. A significant amount of border-trapped charges was observed in both as-deposited and poststressed devices. The kinetics of generation of both oxide-trapped positive charges and interface trapped charges are found to be similar. Both these defects are possibly created by the hydrogen-related species. We demonstrate that compared to devices, HfAlO devices with an equal equivalent oxide thickness (EOT) show better performances in memory and logic applications. On the contrary, at a given stress voltage, the threshold voltage degradation and stress-induced leakage current degradation in HfAlO samples are larger, indicating a shorter device lifetime compared to the samples of the same EOT.

Electrical stress-induced charge carrier generation/trapping related degradation of HfAlO/SiO2 and HfO2/SiO2 gate dielectric stacks

A comparative study on charge carrier generation/trapping and related degradation in HfAlO/SiO2 and HfO2/SiO2 stacks with identical equivalent-oxide-thickness (EOT) is presented during constant gate voltage stress of n-type metal-oxide-semiconductor capacitors. Compared to HfO2 devices, HfAlO devices with an equal EOT show better performances in memory and logic applications. On the contrary, at a given stress voltage, the threshold voltage degradation and stress-induced leakage current degradation in HfAlO samples are higher, indicating shorter device lifetime compared to the HfO2 samples of same EOT. In addition, the mechanism of charge trapping in the oxide as well as at the Si/SiO2 interface of both capacitors is investigated and a model is proposed. A similar generation kinetics was observed for stress-induced oxide trapped positive charges and interface states in either of the devices.

New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate

A detailed analysis of the body potential impact on the performance enhancement of Body Contacted (BC) pMOSFET when the body is not grounded, is reported in this paper. Investigations on BC pMOSFET with a floating-body configuration reveal that this new floating-body effect leads to pMOSFET drive capability increase with higher transconductance, lower subthreshold slope, no off-state leakage current degradation and no kink effect. The body potential is mainly controlled by the electron tunneling from the conduction band (ECB) between the partial n+ poly-gate and the n type silicon substrate through the 1.6 nm thin gate oxide. Static characterizations of various layouts and geometries demonstrate that narrow pMOSFET and H-gate design provides the highest Ion gain due to higher body potential. Furthermore, it has been found that the largest n+ poly-gate area results in the fastest switch-on drain current transients.

Dynamic Characteristics of Metal-Induced Laterally Crystallized Polycrystalline Silicon Thin-Film Transistor Devices and Circuits Fabricated with Asymmetric Precrystallization

The effects of a crystal growth joint in metal-induced laterally crystallized polycrystalline silicon thin-film transistor devices and circuits employing the precrystallization method were studied. It was found that the joint after symmetric precrystallization results in slight degradation in field-effect mobility and little degradation in leakage current, but its location after asymmetric precrystallization has a close connection with degradation only in leakage current and not in mobility. Moreover, DC bias-induced changes in the performance of ring oscillators were studied. Inverters fabricated using a fully asymmetric precrystallized silicon film had very high dynamic and stable performances, compared with inverters fabricated using a symmetric precrystallized silicon film.

Simultaneous Control of the Work Function and Interfacial Oxide Thickness Using Ni∕Hf Stacked Electrode on HfO[sub 2

Both work function and interfacial oxide thickness control were attempted using Ni/Hf bilayered metal electrode on HfO 2 . The flatband voltage, directly related to the work function, with an approximate span of 1 V could be controlled by changing the Hf thickness. The interfacial oxide thickness was decreased with increasing the Hf thickness due to the high reducing capability of the Hf film, and the interface state density was reduced. However, Hf films thinner than 2 nm were needed to avoid the leakage current degradation caused by the diffusion of metallic Hf into the HfO 2 during postdeposition annealing.