Leadframe Packages Research Articles

Achieving Success in Automotive Leadframe Packages

In recent years, the quality and reliability requirements of the automotive market have increased significantly. Among other things, automotive customers are demanding zero defects and zero delamination after extended reliability testing. To support these market requirements,Amkor has invested and continues to invest substantial resources in two strategic directions. The first strategic direction is the development of automation tools to significantly reduce escaped defects and achieve zero delamination. Defect trapping/isolation has been improved by marking tracking identification on leadframe strips prior to the start of assembly. The tracking marks are then used to create defect maps when automatic optical inspection (AOI) is performed following wire bonding and again during open and short (O/S) electrical testing after the completion of assembly. In addition to preventing defective parts from escaping, these automatic inspections provide rapid feedback to the process engineering team in the factory. In the case of the defects caught at AOI, there is a photographic record of all defects found that the engineering team can use to troubleshoot the issue without the need for further failure analysis. As a part of the plan for extending automation implementation for the automotive market, Amkor is currently developing support for Die Traceability Systems (DTS) for leadframe products. DTS leverages the equipment and processes put in place to support defect trapping with the addition of the integration of the die attach equipment with the strip mark tracking to link the customer electronic wafer map to leadframe strip maps. This creates a record of which die are placed on which leadframe locations. The unit laser markers near the end of the assembly process then mark a 2D code on the package identifying the package and linking it to the information about the die and wafer as well as the defect maps generated during the assembly process. The DTS records will be electronically transferred to customers as needed. The second strategic direction has been the development of the capability for leadframe packages to consistently achieve zero delamination following extended automotive reliability (AEC Q100 & Q006 G1 & G0) testing. Many different combinations of processes and materials were tried before consistent results were achieved. With the initial success of these efforts, further implementation is occurring across the broad portfolio of leadframe packages. This success has been achieved by focusing on many factors including design, process and environmental controls, and the interactions of physical properties of the bill of materials (BOM) elements. This paper discusses these strategic directions in greater detail.

The advanced leadless leadframe package and its characteristics

PurposeThe purpose of this study is to offer the advanced leadless leadframe package which achieve small form factor and high thermal and electrical performance, according to the continuous market requirement. Because of demand and trends, new package structures that can accommodate many pins (I/Os) while maintaining the excellent thermal and electrical properties of the leadframe package was studied. Different from conventional leadframe and laminate packages, it must have the large-exposed pad for thermal dissipation and design flexibility to deploy signal, ground and power selectively.Design/methodology/approachIn this study, the routable molded leadframe (rtMLF®) package applying the pre-resin MLF substrate was introduced. The structural advantages, in terms of design flexibility, were checked by adopting the specific electrical feature. Also, the excellence of thermal and electrical performance was confirmed by simulation. The sample was manufactured, and its package robustness was validated by reliability test.FindingsrtMLF package that enables one layer substrate but routable pattern on top layer differently from existing leadframe package was developed and studied if it overcome the limitations of leadframe and laminate products. Asymmetric land layout was designed and special features to keep electrical interference was applied to prove design flexibility. The thermal and electrical simulation has been executed to check the advantages. And key differentiations were identified. Finally, actual sample was manufactured, and structural robustness was validated by package level and board level reliability.Originality/valueThe differentiation of new semiconductor package was introduced and its excellence was verified by electrical and thermal simulation as well as reliability test. It is expected to be adopted for alternative solutions not covered by the existing products.

Packaging design and thermal analysis for 1 mm2 high power VCSEL

PurposeVertical-cavity surface-emitting laser (VCSEL) is a high-performance semiconductor device made of unique epitaxial layers grown on n-type GaAs or InP substrates. The VCSEL’s thermal resistance, Rth, is an essential metric that reflects its thermal properties and dependability. The purpose of this paper is to develop packaging for 1 mm2 VCSEL chips made of a variety of materials, such as ceramic, lead frame and printed circuit board (PCB)-based packaging, as well as provide an idea or design that can withstand and perform well in terms of Rth and heat dissipation during operation. SolidWorks 2017 and AutoCAD Mechanical 2017 software were used to publish all thoughts and ideas, including the size dimensions (x, y and z) and material choices for each package.Design/methodology/approachFollowing the modelling and material selection, the next step is to use the Ansys Mechanical Structural FEA Analysis software to simulate all packaging for Rth and determine which packaging produced the best result, therefore, determining the heat dissipation for each packing. All parameters were used based on the standard cleanroom requirement for the industrial manufacturing backend process, where the cleanroom classification is 10,000 particles (ISO 7). The results demonstrated that the ceramic and lead frame provided good Rth values of 7.3 and 7.0 K/W, respectively, when compared to the PCB, which provided more than 80 K/W; thus, the heat dissipation for PCB packaging also increased.FindingsAs a result of the research, it was determined that ceramic and lead frame packaging are appropriate and capable of delivering good Rth and heat dissipation values when compared to PCB. In comparison to PCB, which requires numerous modifications, such as adding via holes and a thermal bar in an attempt to lower the Rth value, neither packaging requires improvement. Ceramic was chosen for development based on Rth's highest performance, with the actual device consisting of a lead frame and PCB. The Zth measurement test was carried out on a ceramic package, and the Rth result was comparable to the simulation result of 7.6 K/W, indicating that simulation was already proved for research and development.Originality/valueThe purpose of this study is to determine which proposed packaging design would give the highest Rth performance of a 1 mm2 chip as well as the best heat dissipation. In comparison to other studies, VCSEL packaging used the header and window cap as package components with a wavelength of 850 nm, and other VCSEL packaging developments used the sub mount on ceramic package with an output power ranging from 500 mW to 2 W, whereas this study used a huge wavelength and an output power of 4 W.

Wettable flank routable thin MicroLeadFrame for automotive applications

Driven by the higher power density and harsh environments in automotive, leadframe package has been varied to meet the higher requirement of reliability and integration. Quad Flat No-Lead (QFN) packages is known to provide the small form factor, and adequate for the high power package system. However, due to its wet pad characteristics, the solder volume is thin without fillet endangering the structural reliability. Therefore, it is very important to ensure structural integrity by constructing sound solder fillet, and it is mandatory for industry to inspect visually the soldering state after the bonding process. Wettable flank QFN is designed for this particular purpose. In this study, the routable thin MicroLeadFrame®, an wettable flank technology which allows easy process by employing chemical etching yet enables the side solder visible inspection for fine lead pitch, is introduced and explored. Process to achieve the wettable flank structure was developed, and the reliability was studied through Automotive Electronics Council (AEC) reliability test under package level and board level. Also, mechanical shear test and simulation was carries out to verify the wettable flank structure feasibility to the automotive electronics packaging by demonstrating excellent reliability performances.

EMI shielding leadless package solution for automotive

As components get closer together and more devices are integrated into a package, electromagnetic interference (EMI) is one of the most common concerns to be addressed. EMI shielding is not a new topic and its technology has widely been applied to consumer/communication products. However, mainstream products for the automotive market have no clear solution yet. Although leadframe packages, such as Microleadframe® (MLF®)/QFN, are extremely popular for automotive, it is hard to apply EMI technology at the package level because the leads are exposed at the side.In this paper, EMI shielding technology that can be applied to leadframe packages has been studied with the routable MLF (rtMLF®) package. A package structure and layout that give full EMI shielding coverage including the leads is proposed. The shield effectiveness was compared by simulation tests between MLF and RtMLF packages. Also, actual samples were manufactured that confirmed the process and revealed no abnormalities in the conformal shield layer.

Modeling Study on the Impact of Mold Thickness on Strip Warpage of a Molded Leadframe Package

Strip warpage is a common problem in molded leadframe packages. When warpage becomes excessive, the strip could not be processed as it would result in the strip being stuck or damaged during loading to the handling machine loader. This study focuses on the impact of mold cap thickness on strip warpage of a molded Quad Flat No Lead (QFN) package to provide guidance in reducing the strip warpage to an acceptable level. Different mold thickness values were considered in the modeling using finite element analysis (FEA). Results showed that there is an optimum mold thickness, which is around 1.0 mm for 0.20 mm leadframe thickness and 0.65 mm for 0.125 mm leadframe thickness, that gives the lowest warpage in the case considered. The optimum mold cap thickness is lower for thinner leadframe. At mold thickness lower than the optimum value, warpage is in “frowning” mode and increases as the package gets thinner and this agrees with actual observations. This study shows that mold cap thickness has significant impact on molded strip warpage and could be assessed using FEA. Therefore, controlling the mold cap thickness could now be considered an option to reduce strip warpage in molded semiconductor packages as supported by modeling.

Enhanced Die Attach Process Defect Recognition on QFN Leadframe Packages

Advanced packaging at the back-end semiconductor manufacturing characterizes various equipment capabilities per device requirement. High resolution imaging for inspection system during die attach process has gained its interest to feature automated selections during in-line processing. Increasing yet stringent requisites of today’s applications give us leading indicators of market’s demand at more functionality in a smaller and complex package. In light with the technology trend, vision inspection system is a well-known challenge. Instead of using a high magnification microscope off-line after assembly processing, leadframe inspection feature uses optical image-based system to recognize real-time feedback on lead-related defects. Such leadframe inspection activation provides good accuracy, monitoring process integrity in real-time for quad-flat no-leads (QFN) leadframe packages. This paper presents how leadframe inspection at die attach machine takes advantage of simultaneous detection of early die attach defect manifestations.

Modeling of Leadframe Strip Warpage after Die Attach Cure Process

In the leadframe package assembly process, silicon die is attached to the leadframe using a die attach adhesive material and the bonded strip is then cured. However, excessive strip warpage after the die attach cure process is a challenging problem that also affects the succeeding assembly processes. In this study, strip warpage modeling was done using a finite element analysis (FEA) technique to understand the warpage mechanism after die attach cure and find options to reduce strip warpage. The effect of changing the leadframe thickness, die thickness, and the leadframe design in terms of the number of strip panels or changing the connecting bar was analyzed. Modeling demonstrated that lead frame contracts faster than the silicon die resulting in the “frowning” warpage that agrees with the actual observation. It was also shown that increasing the die thickness by 25% results in 27% warpage reduction. Results also showed that increasing the number of panels or maps in a strip could significantly reduce the strip warpage. Improving the panel-to-panel isolation using stress relief cuts is also another option to reduce warpage after die attach cure.

Modeling Study on the Solder Joint Reliability of a Leadframe Package under Powered Thermal Cycling

This paper aims to present a thermo-mechanical modeling approach to predict the solder joint reliability of a leadframe-based package under powered thermal cycling (PTC) test from -40oC to 105oC. The study involves modeling the PTC condition as a standard thermal cycling with a modified temperature boundary to account for the temperature increase due to the applied power to the device package mounted on board. The temperature ramp and dwell times were maintained. Based on the finite element analysis (FEA) results and comparison with actual data, modeling a PTC as a modified thermal cycling process provides a good prediction of the solder joint life. The analysis is simpler and would be beneficial for getting quick assessments of new leadframe package designs.

Understanding Package Crack Signatures in a Leadframe Semiconductor Package

This paper presents the simulation approach used to understand package crack signatures of a leadframe package under different mechanical loading scenarios. Package crack is one of the common problems with semiconductor packages. A better understanding of the different crack signatures would help identify the root cause quickly and be able to find the correct solution. In this study, a high precision materials testing system was used to apply mechanical loading to the package simulating different scenarios that could produce the crack. Based on the testing results, cracks have distinct signatures depending on how the force is applied. With the different signatures identified, this approach makes it easy to find the root cause of the crack in actual applications or assembly processes and resolve the problem faster.

Augmented Leadframe Design for Stable Multi-Wire Ground Bonding

Technological change has brought the global market into broad industrialization and modernization. One major application in the semiconductor industry demands safety and high reliability with strict compliance requirement. This technical paper focuses on the package design solution of quad-flat no leads (QFN) to mitigate the leadframe bouncing and its consequent effect of lifted wire and/or non-stick on leads (NSOL) defects on multi-wire ground connection. Multi-wire on single lead ground (or simply Gnd) connection plays critical attribute in the test coverage risk assessment. Cases of missing wire and/or NSOL on the multi-wire Gnd connection cannot be detected at test resulting to Bin1 (good) instead of Bin5 (open) failure. To ease the failure modes mechanism, a new design of QFN leadframe package with lead-to-diepad bridge-type connection was conceptualized for device with extended leads and with multiple Gnd wires connection. The augmented design would provide better stability than the existing leadframe configurations during wirebonding. Ultimately, the design would help eliminate potential escapees at test of lifted Gnd wire not detected.

Elimination of Crumpled Leadframe Defect through Machine Sensor Enhancement

The paper focused on the improvement done in quad-flat no-leads (QFN) leadframe package assembly to address the quantity of rejection of crumpled leadframe during handling at wirebond process station. Overload sensor at the output magazine handler was found out to be defective, hence a new sensor was installed. With the improvement done, crumpled leadframe strip occurrence was ultimately eliminated.

Multi-Hole Process Plate Modification for Chip on Lead Device at Die Attach Process

The paper focused on the improvement done in chip on lead (COL) leadframe package assembly manufacturing to address the leadframe bouncing effect during die attach process. A new and enhanced process plate is designed with multi-hole configuration to provide a strong vacuum underneath the leadframe and to maintain the planarity during dispensing and die bonding of silicon dies onto the leadframe. With the new multi-hole process plate, leadframe bouncing was successfully eliminated during die attach process. For future works, the multi-hole process plate could be used on devices with similar configuration.

Ball Misplace Mitigation through Process Optimization of Advanced Leadframe Package

One of the challenging assembly processes in semiconductor manufacturing industry is stencil printing using solder paste as direct material. With this technology, some issues were encountered during the development phase of an advanced leadframe device and one of which is the solder ball misplace or off-centered ball. This paper, hence, focused on addressing the ball misplace issue at stencil printing process. Comprehensive parameter optimization particularly on the print speed and print force was employed to eliminate or significantly reduce the ball misplace defect at stencil printing process. With this process optimization and improvement, a reduction of around 96 percent ball misplace occurrence was achieved.

A Study of Die Shear Test Performance on Different Diebond Machine Platforms

The paper focused on the evaluation of quad-flat no-leads single-row (QFN-sr) leadframe package for die shear test performance on different diebond machine platforms. Die shear test determines the adhesion strength on the interface between the silicon die and the die attach glue to the diepad of the leadframe device. Moreover, the test is critically monitored as failed response may lead to die lift or delamination. Statistical results showed the two diebond machines achieving die shear test performance above the specification, with Machine Y having significant improvement over its counterpart. Future works could utilize any of the two diebond machines platforms as far as die shear test performance is concerned. For devices with critical requirement, Machine Y is recommended for its higher die shear test performance capability.

Lead Scratch Resolution through Wirebonding Process Optimization on QFN Packages

With the continuous trend of new technologies in semiconductor manufacturing assembly, challenges and issues are unavoidable. This paper presents an improvement done in quad-flat no-leads (QFN) leadframe package to resolve the quantity of unit rejection due to leads scratch underneath the leadframe. Moreover, the reject manifestation was captured after wirebonding process. Parameter optimization particularly for the second bond with the combination of bond force and bond scrubbing parameters was done to totally eliminate this type of issue after wirebonding process. With the wirebonding process optimization and improvement done, a reduction of 95 percent of leads scratch occurrence was achieved.

ESD Diode Protection Incorporated on Leadframe Package

With the new die technology becomes smaller and thinner, silicon die circuit metallization also becomes smaller, thus electronic devices like quad-flat no-leads multi-row (QFN-mr) semiconductor leadframe package design become more sensitive and prone to electrostatic discharge (ESD) damages. This paper focused and introduced an additional surface mount technology by attaching diodes before and after diebonding process to protect the whole package and to prevent package related issues encountered. With this diode attached on the silicon die and leads, added protection could be achieved on the integrated circuit (IC) mounted on the circuit board level.

Specialized Lead Design of Leadframe Packages for Improved Mold Adhesion

This paper presents an advanced design of Quad-Flat No-leads (QFN) and Quad-Flat Package (QFP) leadframe to mitigate the propagation of delamination between high stress level areas particularly the mold-to-leads interface. The integration of through-hole mechanism on leadframe provides mechanical anchoring of mold material to the lead junction interface and/or vice versa. To produce interlocking, the through-hole design will be penetrated by the epoxy mold compound during conventional molding process affixing each individual lead to the encapsulation material. On the other hand, the package design is materialized through repeated cycle of chemical etching and masking process during leadframe manufacturing, the mechanical anchoring can be implemented on the conventional design of carriers. This approach, considering the design and assembly method of the new leadframe design, is a cost-effective alternative in improving the interfaces of key material such as mold and leadframe.

Die Attach Process Optimization with Enhanced Epoxy Control on Leadframe Package

The paper presents a practical procedure in selecting the best candidate for die attach epoxy control or anti-epoxy bleed-out (anti-EBO) concentration during the introduction of new leadframe configuration. Three different criteria were implemented to measure the relative impact of the anti-EBO into the different interfaces inside a quad-flat no-leads multi-row (QFN-mr) leadframe unit. Die shear test is performed to measure the shear strength and the compatibility of the anti-EBO to the adhesive material. EBO measurement is performed herewith to study the propagation of epoxy bleed-out on the surface of the leadframe with reference to the different level of anti-EBO concentration. Package reliability is employed study the response of different interfaces directly in-contact with anti-EBO through thermal-cycling scenario. Ultimately, understanding the effect of anti-EBO into different set of tests provided a systematic way of selecting appropriate leadframe parameters for QFN-mr leadframe product.

Wafer Saw Process Optimization for Die Chipping Mitigation on Extremely Small Leadframe Package

The paper focused in addressing the silicon die chippings defect at the wafer sawing process of an extremely small semiconductor package. In-depth potential risk analysis and Pareto diagram were done to identify the top reject contributors and eventually resolve the issue. A comprehensive design of experiment (DOE) was done and validation of the solution was employed to formulate the effective corrective actions. Results revealed that die chippings were addressed by optimizing the wafer sawing process through enabling the dressing, pre-cut and step-cutting modes. Ultimately, an improvement of 95% for die chippings reduction was achieved.