Lead-free Solder Interconnects Research Articles

Durability of Lead-Free Solder Interconnections for Printed Circuit Board Applications: Comparing Energy-Based Thermo-Mechanical Fatigue Models

Fatigue models for predicting the cycles to failure of solder interconnections under temperature cycling situations have been discussed and developed for decades. However, most models were developed for different solder materials, components, and printed circuit boards. No previous work has systematically compared these models. Therefore, the variability of their durability predictions is unknown. This study compared nine existing low-cycle energy-based fatigue models for different solder materials and components and then analyzed the differences among them. Each fatigue model had a specific combination of the factors that affect the strain energy density accumulation. Therefore, we adjusted the strain energy density (input) and the predicted cycles to failure (output) in a consistent way to compare the selected fatigue models on the same basis. The differences among the predictions on cycles to failure from the fatigue models was significantly reduced after applying the adjustments, and they exhibited excellent consistency around 1 mJ/mm 3 strain energy density. In the end, factors that can affect the prediction consistency of fatigue mode were provided, including the number of data points while building the fatigue model, the range of strain energy density while selecting the electronic components, and the application of volume-weighted averaging technique on the critical solder joint.

Improving the reliability of power modules through layered diffusion solder interconnects – Comparative study based on experiments and FE-simulation

The demand for reliable, lead-free and high temperature stable solder interconnects for power electronic application has increased in recent years. The die attach solder materials are exposed to higher electrical currents and temperatures due to advancing designs and wide band-gap semiconductors. The diffusion soldering material Sn-Cu-Sn with its high post processing melting temperature is a promising option for high temperature die attach interconnects. The aim of this work is to predict potential failure mechanisms in the die attach of automotive power modules due to simulation based thermo-mechanical analysis of the diffusion solder Sn-Cu-Sn layer and SAC. The FE-model is validated with experimental results from active power cycling tests. The simulation indicates a potential for lifetime increase by usage of layered diffusion solder. The created FE-simulation model could be used for simulation-based design for reliability to reduce material costs and development time.

Nonlinear finite element simulations on the mechanical response of the isothermally aged lead-free solders

The mechanical response, material properties, and mechanical failures of the lead-free solder interconnects continuously evolves and changes due to the isothermal ageing process and during thermal cycling. Therefore, it is very important to include such evolution behavior in the finite element-based evaluations of the solder thermal fatigue life analysis. The current article aims to investigate the effect of the pre-isothermal ageing on the mechanical response of the thermally cycled SAC305 lead-free interconnects utilizing finite element analysis and literature-based material parameters. Additionally, this article explores the solder creep response using two common constitutive laws, Anand and Garofalo models. The simulation results showed that the solder mechanical behavior due to thermal cycling is strongly driven by the ageing process especially for shorter time of ageing. Nonetheless, this effect becomes less effective for prolonged ageing periods. Moreover, the numerical computations proved that the solder response becomes mainly dominated by secondary creep rather than viscoplasticity when the solders are exposed to longer ageing durations. Finally, a detailed discussion on the effect of the pre-ageing process on solder plastic strains and inelastic strain energy density and hence the thermal fatigue life is presented.

Mechanics of solder/IMC interface of lead-free solder interconnects in ball grid array assembly

The lead-free Sn-0.4Ag-0.5Cu (SAC405) solder arrays provides an interconnection between the electronic package and printed circuit board (PCB) of the assembly. The ball grid array (BGA) test assembly was exposed to thermo-mechanical loading during solder reflow cooling and subsequent reliability temperature cycles. This could contribute to the solder/IMC interface damage and cracking. Finite element (FE) analysis was utilized to model the BGA assembly under the prescribed temperature loading profile. The unified constitutive (Anand) model was used to describe the temperature- and strain rate-dependent response, and solder/IMC interface damage of the SAC405 solder interconnects. Solder reflow cooling begins from the assumed stress-free reflow temperature of 220 °C to 25 °C at 1.3 °C/s. This was followed by temperature cycling between 125 and -40 °C with 15 minutes dwell time at upper and lower peak temperature levels. The temperature ramp rate of 11 °C/min was used. Results show that the most critically stressed solder joint was the one located underneath the edge of the silicon die. The solder/IMC interface crack initiated at the interface near the package side of the assembly. Catastrophic fracture of the BGA assembly was predicted during the first temperature cycle due to the relatively low input strength and toughness of the brittle-like solder/IMC interface properties. The solder/IMC failure prediction could not be inferred solely from inelastic strain in the bulk solder joint but should also consider the damage of the interface. This study shall benefit the newly designed BGA packages through rapid generation of reliability data and by providing insight into the reliability aspects of the BGA assembly with interface fracture issues.

Crystalline Silicon (c-Si) Solar Cell Interconnect Damage Prediction Function Based on Effect of Temperature Ramps and Dwells on Creep Damage under Field Thermal Cycling

c-Si solar cell interconnection damages from thermal cycles emanate from cumulative damage contributions from the various load steps in a typical thermal cycle. In general, a typical thermal cycle involves five thermal load steps, namely: 1st cold dwell, ramp-up, hot dwell, ramp-down, and 2nd cold dwell. To predict the contributions of each of these load steps to creep damage in soldered interconnections, each of the respective load steps needs to be profiled to accurately fit a function capable of predicting the damage contributions from a given number of thermal cycles. In this study, a field thermal cycle profile generated from in situ thermal cyclings at a test site in Kumasi, a hot humid region of sub-Saharan Africa, is used to predict damage in solar cell interconnections from accumulated creep energy density using finite element analysis (FEA). The damage was assessed for two different solder formulations, namely: Pb60Sn40 and Sn3.8Ag0.7Cu (lead-free). The results from the FEA simulations show that the cooling (ramp-down) load steps accounted for the highest accumulated creep energy density (ACED) damage in solder interconnections. The ramp-up load steps followed this closely. The cumulative contributions of the two load steps accounted for 78% and 88% of the total damage per cycle in the Pb60Sn40 and Sn3.8Ag0.7Cu solder interconnections, respectively. Furthermore, a study of the damage profiles from each of the five load steps revealed that each of the damage functions from the various load steps is a step function involving the first two thermal cycles, on one hand, and the remaining 10 thermal cycles on the other hand. The damage from the first two thermal cycles can be predicted from a logarithmic function, whereas the damage from the remaining 10 thermal cycles is predicted using six-order polynomial functions. The ACED results computed from the damage functions are in close agreement with the results from the FEA simulation. The functions generated provide useful relations for the prediction of the life (number of cycles to failure) of solder interconnections in solar cells. The systematic approach used in this study can be repeated for other test sites to generate damage functions for the prediction of the life of c-Si PV cells with SnPb and lead-free solder interconnections.

Effect of voids on thermomechanical cracking in lead-free Sn3Ag0.5Cu interconnections of power modules

In this article, the effect of voids on thermomechanically-induced failure in the lead-free solder interconnections of power amplifier (PA) modules is investigated. The interconnection of interest is between the module's flange and substrate (baseplate) initially having a large contact area, and whose cracking has strong detrimental effects on the RF performance and reliability of the PA. PA modules were attached onto baseplates with lead-free SAC305 solder and put to a thermal cycling test (TCT) in the 15 °C to 95 °C range. X-ray imaging was used to characterize the number of voids in interconnections after reflow soldering. The cross-sections of the pristine reflow-soldered and tested interconnections were inspected with cross-polarized light microscopy to reveal the shapes of the voids and crack paths. It was noted that the voids forming in interconnections during the final stages of the reflow process take an elliptical shape, leaning towards the module's outer edge, due to differences in the thermal expansions of the module and baseplate. During the TCT, high thermomechanical stresses caused localized recrystallization of the as-soldered SAC matrix in the vicinity of the elliptical voids. Finally, creep related intergranular cracks formed in these recrystallized areas. Anand's viscoplastic model was used to model the void formation and the effect of the formed voids on crack evolution in solder. Simulations of the high creep energy of the elliptical, tilted voids and their correlation with the recrystallization behavior of the SAC305 interconnections were consistent with the observed creep related failures. Confirmed by simulations, these voids are detrimental to the reliability of solder interconnection because the creep strain is strongly localized to the sharp curvatures of the elliptic void.

Wetting characterization of Flip chip’s Lead-Free Solder Interconnect Using Surface Evolver.

Smaller pitch of first interconnect has posed various challenges to the electronic packaging. The driver to smaller pitch was driven by package and die size miniaturization. In order to enable smaller pitch of first interconnection, copper pillar was introduced. In this paper, surface evolver software was used to predict the solder geometry of solder cap copper pillar onto copper pad process. The study has shown that copper pillar solder joint geometry can be successfully simulated and agreed with experiment. The relationship between various solder joint influencing factors such as die bump diameters, copper pad geometry, solder height and solder volume were established. The optimum die to copper pad width ratio can be obtained through this simulation work. The information can be used to estimate critical volume of solder needed for new, smaller pitch die bump and copper pad design which help to save money and time by avoiding a large number of experiments prior to mass production.

Microstructural Indicators for Assessment of Effect of Prolonged and Intermittent Storage on Reliability of Lead-free Electronics

Electronic systems may be subjected to prolonged and intermittent periods of storage prior to deployment or usage. Prior studies have shown that the lead-free solder interconnects show measurable degradation in the mechanical properties even after the brief exposures to high temperature. In this paper, a method has been developed for determining the equivalent storage time to produce identical damage at a different temperature. Electronics subjected to accelerated tests often have a well-defined thermal profile for a specified period of time. Quantification of the thermal profile in field-deployed electronics may be often difficult because of the variance in the environment conditions and usage profile. There is a need for tools and techniques to quantify the damage in deployed systems in the absence of macroindicators of damage without the knowledge of prior stress history. The approach for mapping damage in the lead-free second-level interconnects between different thermal conditions is new. High-reliability applications, such as avionics and missile systems, may be often exposed to long periods of storage prior to deployment. The effect of storage at different temperature conditions can be mapped using the presented approach. A framework has been developed to investigate the system state and estimate the remaining useful life of the solder ball subjected to a variety of isothermal aging conditions, including 60 °C, 75 °C, and 125 °C for periods of time between 1 and 4 weeks. Data on damage precursors, including the rate of change in the normalized phase growth and the normalized IMC thickness, has been collected and analyzed to derive physics-based damage mapping relationships for aging. Mathematical relationships have been derived for the damage mapping to various thermal storage environments to facilitate determining an appropriate time–temperature combination to reach a particular level of damage state. Activation energy for the leading indicators of failure is also computed. Specific damage proxies examined include the phase-growth indicator and the intermetallic thickness. The viability of the approach has been demonstrated for the lead-free test assemblies subjected to multiple thermal aging at 60 °C, 75 °C, and 125 °C. Damage mapping relationships are derived from the data based on the two separate leading indicators.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Reinforced solder joint performance by incorporation of ZrO2 nanoparticles in electroless Ni–P composite layer

Abstract

Effect of carbon nanotubes and their dispersion on electroless Ni–P under bump metallization for lead-free solder interconnection

Electroless Ni–P under bump metallization (UBM) has advantages of even surface, low cost and simplicity to deposit, but their mechanical strength, corrosion resistance and stability still face challenges under high soldering temperature. Incorporating carbon nanotubes (CNTs) into electroless Ni–P UBM might be expected to provide Ni–P–CNT composites with high mechanical strength and stability. Ni–P–CNT composite coatings as well as Ni–P coatings were fabricated by electroless plating process. In order to homogeneously disperse CNTs in composite coatings, acid pre-treatment and surfactant dispersant were introduced. During composite electroless plating, the ultrasonic agitation was also employed. In this study, scanning electronic microscopy (SEM) was used to observe the morphology and the CNTs were proved to be uniformly distributed in Ni–P–CNT coatings by SEM and atomic force microscopy. It was verified that the surface of the composite was quite smooth and continuous; CNTs are equably embedded in the matrix, which is advantageous for conductivity, mechanical strength and corrosion resistance. Shear tests were conducted to evaluate the effect of CNT reinforcement on the mechanical properties of joints, and the joints with CNT additions exhibited higher shear strength at different reflow cycles. Moreover, deposition mechanism of CNTs with Ni was analyzed and confirmed by transmission electron microscopy. Factors that affecting plating process was also discussed, and the optimum plating condition was suggested in this study.

(Invited) Electromigration Reliability of Lead-Free Solder Interconnects

Line-type Cu/Sn/Ni and Cu/Sn/Ni-P interconnects as well as real Ni/Sn3.0Ag0.5Cu/Cu and Ni/Sn3.0Ag0.5Cu/Ni-P flip chip solder joints were comparatively studied to reveal the electromigration reliability of solder joints. The experimental results of the line-type solder interconnects showed that Cu could diffuse to the opposite anode Ni interface and change the interfacial IMC type while Ni could not change IMC type at the opposite anode Cu interface under a current density of 1×104A/cm2 at 150 oC. In real flip chip solder joints, the EM life of Cu (OSP) solder joints was significantly longer than that of Ni-P (ENEPIG) solder joints. A higher Cu content in the solder bumps effectively improved the electromigration resistance of solder joints. This work provides a suggestion for optimizing the structure of flip chip solder joints.

Effect of TiO2 nanoparticle addition on electroless Ni–P under bump metallization for lead-free solder interconnection

One primary purpose of this study is to introduce an electroless Ni–P–TiO2 (17.5at% of P) composite coating as a pad finish for advanced electronic packaging. In this study, TiO2 nanoparticles were incorporated into the Ni–P layer by electroless deposition and its function as novel under bump metallization (UBM) was intensively investigated. The majority of the added TiO2 nanoparticles were proved to be uniformly distributed in UBM by scanning electronic microscopy (SEM) and X-ray diffraction (XRD). The interfacial reaction between electrolessly deposited Ni–P–TiO2 layer and Sn–3.5Ag solder alloy was systematically analyzed. The prime Ni–P UBM was used for comparison to evaluate the effect of TiO2 nanoparticle on the interfacial microstructure and mechanical property. Both solder/Ni–P and solder/Ni–P–TiO2 joints were aged at temperature from 150°C to 190°C for different aging periods in order to study the intermetallic compounds (IMCs) growth and calculate the activation energy. It was found the growth of Ni3Sn4 IMC layer and the void formation at the reaction interface were successfully suppressed with the help of the TiO2 nanoparticle. The activation energies for the growth of Ni3Sn4 on Ni–P and Ni–P–TiO2 layers were calculated to be 50.9kJ/mol and 55.7kJ/mol, respectively. The extensive growth of Ni3P and Ni–Sn–P phases as well as the consumption rate of the amorphous UBM was controlled in joints with TiO2 nanoparticles. Thus Ni–P–TiO2 UBM blocked the Cu diffusion from substrate to interface. A detailed reaction induced diffusion mechanism was proposed. The solder/Ni–P–TiO2 solder joint consistently demonstrated higher shear strength than solder/Ni–P joint as a function of aging time. TiO2 nanoparticle contributed to slow down the declining rate of shear strength from 0.021Mpa/h to 0.013Mpa/h with the aging time. Moreover, after the shear strength test, fracture mainly occurred at solder matrix of the solder/Ni–P–TiO2 joint; the morphology showed a ductile fracture pattern with a large distribution of dimples on the rough surface.

Cohesive fracture mechanics based numerical analysis to BGA packaging and lead free solders under drop impact

Lead free solders are replacing lead rich solders in the electronic industry, the performance and safety of lead free solder interconnects in electric packaging under drop impact becomes a critical concern of semiconductor and electronic product manufacturers. Compared with the lead rich solder alloy, lead free solder alloy typically has higher rigidity and lower ductility. The presence of the Intermetallic Compound (IMC) layer can also affect the drop impact response of the solder interconnect, which may lead to quasi-brittle solder/IMC interfacial fracture. The traditional drop test is expensive and time consuming, and it is quite difficult to observe the full dynamic responses during the drop impact. In the present study, numerical analysis is performed to investigate drop impact effect on ball grid array (BGA) electronic packaging with the intention of predicting the performance of solders under drop impact and providing the fundamental understanding required to design a reliable electric packaging. A three dimensional finite element model is developed to simulate the solder interconnect and electronic packaging failure under board-level drop impact. An impact analysis procedure coupled with sub-modeling technique is established. The Cu6Sn5 and Cu3Sn IMC layers are incorporated in the solder interconnects model; cohesive fracture mechanics based method is applied to predict the crack initiation and propagation near the IMC/solder interface. A lead-free solder alloy constitutive relationship comprising elastic and rate dependent plastic effects is incorporated in the computational model.

Localized recrystallization and cracking of lead-free solder interconnections under thermal cycling – ERRATUM

Localized recrystallization and cracking of lead-free solder interconnections under thermal cycling – <b>ERRATUM</b>

Localized recrystallization and cracking of lead-free solder interconnections under thermal cycling

Abstract

Drop Performance of Land Grid Array Packages as a Function of Cu Content in Lead-free Solder Alloys

High strain-rate drop impact tests were performed for land grid array (LGA) packages with (electroless nickel immersion gold) ENIG metallization and lead-free solder interconnects. Sn-4Ag-0.5Cu (in wt%, SAC405), Sn-3.5Ag (in wt%), and Sn-0.7Cu (in wt%) were used for pretinning the LGA pads. SAC 405 alloy was used for the LGA-to-board mounting. Drop test results showed two distinct trends. Samples pretinned with Sn-4Ag-0.5Cu and Sn-3.5Ag showed poor drop performance while those pretinned with Sn-0.7Cu (in wt%) or without pretinning showed excellent drop performance. The dierence in behavior is related to the initial intermetallic morphology and structure. The needle shape Ni3Sn4-based intermetallics were observed for the first two cases. This led to poor adhesion between solder and NiP metallization. The samples with Sn-0.7Cu pretinning and no pretinning showed a continuous intermetallic morphology. In this case, sucient Cu improved the solder wetting and formed a continuous intermetallic morphology, leading to better drop performance. A sucient amount of Cu makes the better wetting, forming (Cu,Ni)

Effect of Constant and Cyclic Current Stressing on the Evolution of Intermetallic Compound Layers

In this paper the effects of constant and cyclic power loads on the evolution of interfacial reaction layers in lead-free solder interconnections are presented. Firstly, the differences in the growth behavior of intermetallic compound (IMC) layers at the cathode and anode sides of the interconnections are rationalized. This is done by considering the changes in the intrinsic fluxes of elements owing to electromigration as well as taking into account the fact that the growth of Cu3Sn and Cu6Sn5 are coupled via interfacial reactions. In this way, better understanding of the effect of electron flux on the growth of each individual layer in the Cu-Sn system can be achieved. Secondly, it is shown that there is a distinct difference between steady-state current stressing (constant current, constant temperature) and power cycling with alternating on- and off-cycle periods (accompanied by a change of temperature). The reasons behind the observed differences are subsequently discussed. Finally, special care is taken to ensure that the current densities are chosen in such a way that there is no risk for even partial melting of the solder interconnections.

Development Trend of Three-Dimensional (3D) Integration Technology

Over the past decades, the downscaling of transistor dimensions has improved circuit performance, power, and integration density. However, conventional device scaling is approaching the physical limits and it is increasingly difficult to sustain the same miniaturization scaling rate. Three-dimensional (3D) integrated circuits that stack multiple functional chips using through-silicon-vias (TSVs) and low-volume lead-free solder interconnects may overcome these problems, because this approach makes it possible to reduce global interconnect length and to increase device density without shrinking device dimensions. Different levels of 3D integration investigation were previously reported and updated. The current paper reviews the 3D integration technologies, including process technology and reliability characterization.

Simulation of dynamic recrystallization in solder interconnections during thermal cycling

In the present study, an algorithm, combining the Potts model based Monte Carlo (MC) and finite element methods, is developed in order to predict the dynamic recrystallization of tin in tin-rich lead-free solder interconnections during thermal cycling. A correlation between real time and MC simulation time is established. The phenomenon that intermetallic particles provide favorable sites for nucleation of new tin grains in solder matrix is also simulated. It is demonstrated that the present algorithm predicts the incubation period of the recrystallization as well as the growth tendency of the recrystallized regions, in a way consistent with the experimental findings. This quantitative description of the microstructural changes will contribute significantly to the reliability studies of solder interconnections.