Leadframe Research Articles

In depth study of lead frame tape residuein quad flat non-leaded package

PurposeLead frame tape is a crucial support for lead frames in the IC assembly process. The tape residue on the quad flat non-leaded (QFN) could result in low reliability and failure in electrical conductivity tests. The tape residue would affect overall performance of the chips and contribute to low pass yield. The purpose of this paper is to present an in-depth study of tape residue and factors that may affect it.Design/methodology/approachAn experiment using lead frame and tapes from three manufacturers with two types of die bond adhesives, namely, die attach film (DAF) and wafer back coating (WBC), was conducted. Copper (Cu) wire bonding and die bonding performances were measured in terms of process capability, stitch bond strength and die attach strength.FindingsResults showed that no tape residue was observed on the thermoplastic adhesive-based lead frames manufactured by Hitachi after the de-taping process because of the tape’s thermoplastic adhesive properties.Originality/valueThis paper studies the occurrence of tape residue and a viable solution for it through the correct process optimization and combination of semiconductor manufacturing materials. Factors that may affect tape residue have also been studied and further research can be done to explore other options in the future as an alternate solution.

Effect of Heat treatment on microstructure and properties of Cu-Ni-Co-Si alloy

In the paper, the effect of different solution and aging treatment on microstructure and properties of Cu-Ni-Co-Si alloy is investigated in detail. The results show that the recrystallization, grain growth and second phase solubilization are observed during the continuous solution treatment on line of Cu-Ni-Co-Si alloy. When the Cu-Ni-Co-Si alloy is solutioned at 970 °C and speed of annealing is 10 m/min, aged at 500 °C for 8 h, 40 % cold roll and aged at 325 C for 12 h, it has the excellent comprehensive properties, which can meet the needs of high-end lead frame and connectors. The Disk-shaped precipitates have been confirmed as (Ni, Co)2Si phase. The crystal orientation relationship between matrix and precipitatesis[

Oxidation characteristics of commercial copper-based lead frame surface and the bonding with epoxy molding compounds

This study investigates surface oxidized layers of Cu-Fe-Zn-P (C194) and Cu-Ni-Si-Mg (C7025) lead frames under different oxidation conditions and their influence on the adhesion of epoxy molding compounds with lead frames. Micro-etching and electroplating are adopted to roughen the surface. Isothermal heat treatments which simulate molding and curing processes, as well as high temperature aging, are carried out to oxidize lead frame surface. According to the absorption peaks of FTIR (Fourier transform infrared spectroscopy) spectra, the topmost surface of the oxide layer can be easily identified. In combination with the reduction potential and time obtained from the coulometric reduction test, the variation of oxide phases along the through-thickness direction can also be revealed. Experimental results show that in addition to surface roughness, surface oxides and their thickness play more important roles in the interfacial strength between lead frames and epoxy molding compounds. In the case of the surface with one single Cu2O layer, an increase in oxide layer results in a decrease in bonding strength. Once the topmost surface forms CuO, the bonding strength could be enhanced due to a greater surface energy. Compared with electroplated C194, the thinner surface oxide layer and thus better performance in adhesion strength for electroplated C7025 can be ascribed to the immersion Ag surface treatment.

Strength and electrical conductivity behavior of nanoparticles reaction on new alumina dispersion-strengthened copper alloy

Alumina dispersion-strengthened copper (ADSC) alloy is a new materials widely used in lead frames, resistance welding electrodes, etc. The paper has systematically studied the strength and electrical conductivity behavior in situ reaction using rare-earth La and Ce. Solving the clustering on nanoparticles Al2O3 under spark plasma sintering (SPS) and addition of La and Ce for ADSC alloy is the significant differences. Specimen of Cu-0.7 wt% Al2O3 added with 0.7 wt% Ce does not present pores in SEM and BSE images due to special dispersed element Ce. A new ADSC alloy fabricated with Cu-0.7 wt%Al2O3-0.7 wt% Ce under SPS shows the high -strength and the high-conductivity. Nanoparticles Al2O3 encircled with nanoparticles CeO2 and Cu2O, which is generated in situ are evenly distributed in the Cu matrix, resulting in increasing strength. Lattice distortion does not occur in the new ADSC alloy. Cu atoms are replaced by Al generated in situ to form a solid solution with a face-centered cubic structure owing to the similar atomic radii and electronegativities of Cu and Al, resulting in increasing the electrical conductivity. Experimental results show that adding rare-earth metal nanoparticles Ce can significantly improve the properties of ADSC alloy.

Microstructure and properties of a Cu–Ni–Si–Co–Cr alloy with high strength and high conductivity

A novel Cu-1.01%Ni-0.28%Si-0.14%Co-0.45%Cr (mass percent) alloy with high strength and high conductivity was fabricated. Microstructure, mechanical and electrical properties of the alloy after multi-stage thermo-mechanical treatment were investigated in detail. The alloy has excellent comprehensive properties, with a tensile strength of 810 MPa, yield strength of 777 MPa, elongation of 3.4%, and electrical conductivity of 57.5%IACS (International Annealing Copper Standard). Three kinds of precipitates, (Cr,Co)2Si, (Ni,Co)2Si and Cr, form during aging treatment. Addition of Co element promotes the precipitation of Cr, Ni and Si solute elements from the matrix, while inhibits the growth of the (Cr,Co)2Si. The high strength of the alloy treated by multi-stage thermo-mechanical process is attributed to the dispersion strengthening, sub-structure strengthening, and work-hardening. The multi-aging process and addition of Co effectively improve the electrical conductivity of the studied alloy. The high strength and high conductivity of studied alloy make it as a potential candidate for lead frame materials in electrical and electronics industry.

Comparative Study of Chloride and Fluoride Induced Al Pad Corrosion in Wire Bonded Packaging Assembly

Microelectronics are used in virtually all electronic equipment’s nowadays ranging from medical instruments, automobiles, computers, cell phones and home appliances. Wirebonding process which connects the chip to the lead frame in IC packaging plays a very important role in the commercial production of IC’s. Chip usually consists of Al bond pads with Cu/Au wires. Thin film Al bond pads are easily vulnerable to corrosion in presence of contaminants and moisture. Bond pad corrosion is one of the common modes of corrosion failure in wire-bonded devices IC packaging. Improper rinsing, packaging and passivation defects allows moisture and contaminants into bondpads resulting in severe corrosion. Most common source of this corrosion comes from the presence of halide ions contamination as (Cl-, F-, Br- etc.) However, the corrosion morphology and the severity varies from different ions contamination as the chemistry governing the corrosion differs from one ion to another. Our research is focused on key findings on corrosion of Aluminum bond pad due to chloride (Cl-) and fluoride (F-) contamination. Our central motivation is to identify this F- corrosion mechanism, so that it will help to develop a strategy to prevent it and study the comparison between Cl- and F- Corrosion using Micro-pattern corrosion screening technique, Wire-bonded device (WBD) and other characterization technique such as GC-MS, SEM and tafel. GC-MS reveals that H2 gas evolution is observed during Cl- corrosion of the WBD, whereas little or no H2 evolution is observed during F- corrosion. SEM and EDX reveals no presence of Cl- in the corroded areas of its corrosion, whereas strong F- signal is observed in F- corrosion of the bondpads revealing, that the corrosion products formed on the surface has very poor solubility showing that Cl- and F- has a complete different corrosion morphology. Striking contrasts in corrosion morphology observed during the Cl- and F- corrosion were explained in the present work and will lead to better understanding of factors influencing the bond pad corrosion leading to the wire bond failure in IC packaging devices. [Fig. 1] Figure 1

Development of a New Copper Corrosion Screening Methodology for Application in Microelectronics

Due to the constant miniaturization of microelectronics, the aim of the semiconductor industry has been to increase the packaging density of devices. Wire bonds form the primary interconnects between the integrated circuit chip and the metal lead frame in semiconductor packaging. Gold (Au) wire has been used for wire bonding in the electronics industry because of its mechanical and electrical properties, high reliability, and ease of assembly. However, due to the increasingly high cost of Au, alternative wire bonding materials have been considered. Copper (Cu) is gradually replacing Au because it exhibits not only a high resistance to electromigration, but also has excellent electrical conductivity and a low resistivity. The benefit of copper’s conductivity is that it reduces heat generated by joule heating, thus reducing RC delay. However, copper also has its drawbacks; tiny amounts of contaminant can corrode Cu interconnects, leading to the failure of entire microelectronic devices. On-chip corrosion within Cu interconnect microstructures can result in increased defectiveness, which causes serious reliability issues and decreases production yield. Copper is susceptible to corrode in acidic and strong alkaline solutions in the presence of oxygen and other oxidants. Effective corrosion monitoring is critical as an early alert before the onset of corrosion-related failure. In this study, we report a new method for monitoring the corrosion of copper relevant to the microelectronics industry through the combination of electrical resistance measurement changes of Cu wire and microscopic time-lapse imaging. Industry-grade 99.99% Cu bonding wire (diameter = 25μm) was exposed to the harsh, oxidizing conditions of ammonium persulfate, and its change in resistance was monitored. As the corrosion of Cu bonding wire took place, the cross-sectional area of the wire decreased, causing an increase in its resistance (via R= ρ•l/A). During the resistance monitoring, the simultaneous microscope time-lapse imaging enabled Cu corrosion to be observed in real time. Due to the combined quantitative and qualitative nature of this metrology, it provides detail on the corrosion process that might not be obtained by traditional corrosion tests. While ammonium persulfate will almost never be encountered by an IC device during normal use, it provides a rapid screening environment that can quickly distinguish between corrosion inhibition and no protection at all. This metrology was used to test both bare Cu bonding wire and corrosion-inhibitor coated bonding wire, and showed a drastic difference in their corrosion rate and behavior. This work ultimately aids with inhibitor selection and inhibitor coating design that will help ensure long term reliability of electronics used in industrial applications. Figure 1

A lead-framed glass mirror from a Roman woman's grave in Padua/Patavium (north-eastern Italy) – investigating its function and production with a multidisciplinary approach

Abstract A small Roman mirror, made up of a square lead frame and a convex reflective glass surface, was recently recovered in Padua in a grave dating back to the second half of the 2nd century AD. It was investigated with a multidisciplinary approach. During restoration, the artefact was dismantled, its individual components cleaned, consolidated and then reassembled. Chemical and isotopic analyses were carried out on microscopic fragments from both the glass and the lead components to identify their origin and production technologies. Structured-light 3D scanning was used both to produce a model of the artefact and to reconstruct its optical properties. Archaeometric results show that the 200 μm thick reflective glass surface, coated with a thin lead film, belongs to the Sb-colourless group. The lead frame is now totally oxidised. The lead isotope ratios of both the glass coating and the frame show a common composition, statistically close to some Romanian ores. These data suggest a multistep production process, most likely carried out in the same workshop. The distribution of similar finds mainly between the Northern-Adriatic basin and the Danube could indicate that these products were manufactured in the central-eastern provinces of the Roman Empire, presumably in the Southern Carpathian area, close to the local lead ore deposits. The typology is well defined thanks to the 3D model that is an important tool for morphometric investigations. The optical properties of the mirror, given by its convex spherical surface with a 9 cm radius, suggest the object was actually used as a makeup tool. In conclusion, this multidisciplinary approach reveals that despite its non-precious materials, the mirror can be considered a product of superior technological and scientific skills.

Problemi korozije u elektronskim sistemima

Microelectronics and, chiefly, silicon integrated circuit microelectronics, has created astonishing capabilities over the last 40 years. Speedy advancement in CMOS transistor equipment leading to the gigahertz speeds common today has necessitated chief changes in semiconductor manufacturing technology and the expansion of high frequency compatible packaging. The progress of an optimized formulation for electroless nickel (EN) plating with a long life span to make a deposit with good corrosion resistance (CR). The electroless deposition of Ni-P alloys is widely used in diverse fields such as aerospace, automation, electronics, nuclear, oil and gas production, and valve industries. Lead frame is the primary package metallurgical bond pad interface in microelectronic devices which provides external interconnection. The most predominant lead frame material is copper with tin plating. Over the years, galvanic corrosion and copper oxidation are two major reliability concerns for any microelectronics packages with copper lead frame, when operating under high humidity environment.

The bifurcation of advanced packaging

Following a similar trend from the 1990's, IC package design is experiencing a sea change. As a refresher, the 1990's is when the ball grid array (BGA) came along, introducing a whole new set of design tool requirements. The mechanical design tools used for the previous generation of lead frame styled packages were no longer capable of supporting the new design requirements of the BGA. In short, the BGA introduced multi-layer routable organic and ceramic substrates and new possibilities for stacking (and embedding) multi-die, requiring designers to abandon their mechanical design tools and look at new solutions for doing package design. On top of that, IO's were switching faster than ever, requiring engineers to look at new ways of electrically characterizing these designs. As a result, a couple of EDA companies stepped up and adapted their printed circuit board (PCB) layout and analysis tools for that generation of BGA-based advanced packaging. Problem (more or less) solved! Fast forward to today and we see a very similar trend. Now being introduced at a rapid pace, are new advanced IC packaging solutions that have a lot more silicon content, wafer stacking and, in some cases, chips being packaged directly at the wafer-level at traditional IC foundries, skipping the traditional OSAT model of the past. Make no mistake, this is a significant change to the status quo of BGA package design tools of the past. The PCB-like flows that were established for BGA design are likely not the path forward for technologies like, 2.5D/3D IC and fan-out wafer-level packaging (FOWLP). Instead, in all likelihood IC design tools and flows will need to be slightly adapted to support the next generation of package designs. Let's start with foundry-based FOWLP. In this case, induvial dice are placed on a chip-carrier with additional spacing between them. Molding is poured in the empty space and then an array of bumps (UBM) and the connectivity (RDL) are added. In foundry-based flows, these UBM and RDL layers require IC-styled routing/metal fill and mask generation from the layout tool. In addition, these masks must be verified with traditional IC DRC/LVS tools. It's clear that some kind of hybrid advanced packaging flow using some traditional IC tools in the flow is required to support this type of design. And in fact, if you look at the largest semiconductor foundries reference flow tools, you will find this to be true. This presentation further examines the design tool/flow requirement for FOWLP, 2.5D/3D IC and future multi-die packaging technologies.

FcLGA Package Assembly Qualification for Mobile Applications

Abstract Flip Chip Land Grid Array (FcLGA) packages are widely used in Mobile product applications due to their thin form factor and performance. Assembly process qualification requires careful selection of materials and optimization of reflow processes to make consistent and reliable product. The fcLGA typically uses an organic substrate on which the die is reflowed instead of the copper lead frame used in QFN packages. This requires assessment of CTE mismatch and controlled reflow processes to prevent bump separation [1]. The paper reviews the selection of substrate, optimization of assembly process and reliability testing conducted for package qualification

Correlation between microstructures and mechanical properties of cryorolled CuNiSi alloys with Cr and Zr alloying

Due to their high strength and high electrical conductivity, CuNiSi system alloys are widely used as lead frames and connectors. In this work, CuNiSi alloys alloyed with Cr and Zr were rolled at liquid nitrogen temperature and subjected to various aging treatments. High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) analysis showed that in addition to forming Cr3Si and Ni2SiZr particles, elemental Cr and Zr distributed evenly in the matrix. Ni and Si segregated at the interface between the particles and matrix to form Ni2Si precipitates. During the aging process, Cr alloying increased the hardness while slightly reducing the electrical conductivity of the alloy. This was ascribed to the refined precipitates and hindered precipitation kinetics. Zr alloying promoted both the precipitate growth and the precipitation kinetics of the CuNiSi alloys, while decreasing their hardness and enhancing their electrical conductivity. According to the results of the synchrotron X-ray diffraction (XRD) analysis, Cr alloying increased the dislocation density of CuNiSi alloys and suppressed the annihilation of dislocations during aging. This promoted strength through work hardening. Compared to CuNiSi alloys aged at 723 K for 2 h, the ultimate tensile strength of the alloys obtained after Cr alloying using a two-step rolling aging process was increased by 154 MPa and their electrical conductivity was increased by 4.8% International Annealed Copper Standard (IACS).

Experimental prediction of multi-nozzle spray characteristics for optimal design in a lead frame etching process

The objective of this paper is to provide quantitative information of uniform impact forces on the sprayed surface in order to optimize the multi-nozzle spray etching system. Spray characteristics obtained from optical non-intrusive measurements using particle image velocimetry (PIV) and particle motion analysis system (PMAS) are measured in single- and twin-nozzle sprays, and then the multi-nozzle spray characteristics is simulated based on those of measurement data. The influences of the multi-nozzle arrangement, nozzle pitch, and pipe pitch on the spray characteristics such as droplets’ velocity, diameter, number density, impact force and their uniformity are properly evaluated. The experimental cases E1 and E2 represent single-spray nozzle A and B, respectively. For twin-spray tests, three nozzle combinations, namely E3 (nozzle A-A), E4 (nozzle A-B) and E5 (nozzle B-B) are considered with different nozzle pitches. The multi-spray simulation cases S1 and S6 represent the multi-spray cases with a homo-nozzle arrays which is consisted in all nozzles of nozzle A or B. For cases from case S2 to S5, the multi-spray cases with a hybrid-nozzle arrays which is consisted in all nozzles of nozzle A and B. The results show that the impact force increases approximately twice as much for changing of experimental test cases from E1 to E5 owing to the differences in nozzle characteristics of single-sprays and the overlap region between two adjacent nozzles. For the multi-nozzle spray simulation, the uniformity of impact force (UI) is increased with increasing the number of nozzle B which has larger orifice diameter and a wider spray angle. The optimum multi-nozzle spray arrangement is case S4 with more than 90 % UI, based on the fact that the UI is quite stable with increasing the nozzle pitch ranging from 90 mm to 145 mm.

Comparison of ultrasonic wire bonding process between gold and copper by nonlinear structure analysis

Wire bonding is one of the most important processes which connected the chip and lead frame in microelectronics packaging. Due to the expensive price of gold, copper wire and aluminum wire gradually become the substitutes of gold wire in the process of bonding. Meanwhile, changes in the materials result in a series of problems, such as violent wear of capillary and less reliable production on account of its higher Young modulus. However, the tiny range of parameter values for stable process makes it difficult to do experiment. In order to observe the process of thermalsonic bonding and find out the influence of new material in bonding stage, a transient nonlinear dynamic finite element framework is developed in this paper. A comprehensive parametric study which includes different thickness of bond pad and material of bond wire were conducted in this research to improve the reliability of wire bonding. The comparison between copper and gold wire bonding process on the third generation LEDs is introduced. As a result, this numerical simulation framework is of great importance to the development of LEDs packaging.

Preparation of CuO powder for electroplating using lead frame etching wastes

A novel method for manufacture of copper(II) oxide for copper electroplating solution is proposed in this paper. The copper(II) oxide was produced through two chemical reaction steps without sintering process after refinement of waste lead frame etching solution. The experimental major parameters were the amount of additives for first and second step, sodium carbonate and sodium hydroxide, respectively, to evaluate reaction characteristics. Also, the liquidity (angle of repose), solubility to sulfuric acid, chloric ion concentration and thickness of dimple thickness of plating hole were verified for the physical properties of copper(II) oxide as electroplating material.The reaction molar ratio of sodium carbonate was low, and Cu2CO3 was generated more than Cu(OH)2.The optimum reaction mole ratio of sodium carbonate to copper chloride was revealed as 1.5. The optimum usage of sodium hydroxide for manufacture of copper(II) oxide using basic copper carbonate, produced at first reaction step, was 150g. In these conditions, the average particle size of copper(II) oxide, the dissolution time for sulfuric acid, and the angle of repose were 21.49μm, 62s, and 35.5°, respectively. The yield of copper(II) oxide was 98.0wt.%, for this optimum usage. Also, the via-filling hole thickness was 13.5μm, which satisfies general via-filling hole thickness range, less than 15μm.

In Situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction. Part 3

In Situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction. Part 3

Aging Studies of Cu–Sn Intermetallics in Cu Micropillars Used in Flip Chip Attachment onto Cu Lead Frames

Copper micropillars plated onto a silicon die and soldered with Sn-Ag solder to a copper lead frame in a flip chip on lead package have been subjected to high-temperature storage at 150°C and 175°C for 500 h, 1000 h, and 1500 h. Cu6Sn5 and Cu3Sn intermetallic compounds were found on both sides of the solder, but the growth rates were not the same as evidenced by different values of the growth exponent n. Cu and Sn diffusion controlled the Cu3Sn growth in the Cu pillar interface (n ≈ 0.5), while interface reactions controlled the growth in the Cu lead frame interface (n ≈ 0.8). Increasing the aging temperature increased the growth of Cu3Sn as well as the presence of microvoids in the Cu lead frame side. Adding Ni as a barrier layer on the Cu pillar prevented the growth of Cu3Sn in the Cu pillar interface and reduced its growth rate on the lead frame side, even at higher aging temperatures.

Multi-type Noise Removal in Lead Frame Image Using Enhanced Hybrid Median Filter

Image filtering technique plays a very important role in digital image processing. It is one of the major steps in image enhancement and restoration. This filtering technique can remove noise and preserve the details of the image for feature extraction processes. However, filtering process can still be considered as a huge challenge for image filtering technique. Common noises in the image such as Salt & Pepper, Gaussian, Speckle, and Poisson Noise are still posing problems in filtering process where the quality and the originality of the images can be degraded and disturbed. Meanwhile, a single filtering technique is usually fit to deal with only certain specific noise. This paper presents an enhanced Hybrid Median Filter (H6F) technique to improve image filtering process. The technique involves 3x3 sub-mask and determination of new pixel value from the median value of the three steps which are the median calculation of ‘+’-neighbours, median calculation of all sub-masks and selection of centre pixel value. The H6F technique has been computed on lead frame inspection system. The results have shown that the technique has been able to remove multi-type of noises efficiently and produce exceptionally low Mean-Square Error (MSE) while consuming the acceptable amount of execution time when compared to other filtering techniques.

Next Generation Chip Embedding Technology for High Efficient Mid Power Modules

Abstract Embedding active dies into the substrate is fulfilling integration requirements for modern communication devices, and furthermore embedding was shown to have beneficial effects on electrical performance and thermal dissipation, especially for mid power modules (from a few hundred watts to 5kW) [1–3]. It comes with strong advantages as the power modules operate at higher frequencies (MHz range) and aim to apply smaller capacitors and inductors. This approach reduces the overall PCB size and weight from system point of view. These beneficial effects were observed especially for embedded power dies that were already mounted in a lead frame cavity when embedding [3]. In this paper we shall report the development of embedded technologies for power modules mounted in a lead frame cavity and compare electrical performance, thermal dissipation and reliability results with conventional PQFN packaging [3]. We shall also report electrical performance in various operation frequency ranges from a few kHz to MHz to address the benefit on high switching frequency power modules for SiC or GaN applications. We will also address if the EMI effect can be eliminated by using chip embedded technology instead of wire bonding connection from driver to gate pad of power MOSFET chip. We will conclude that the challenges of electrical performance and thermal dissipation required for today's power modules can successfully be overcome by next generation power modules based on lead frame chip embedding.

Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

This research studied about effecting aging time of epoxy molding compound (EMC) that effect to reliability performance of integrated circuit (IC) package in molding process. Molding process is so important of IC packaging process for protecting IC chip (or die) from temperature and humidity environment using encapsulated EMC. For general molding process, EMC are stored in the frozen at 5°C and left at room temperature at 25 °C for aging time on self before molding of die onto lead frame is 24 hours. The aging time effect to reliability performance of IC package due to different temperature and humidity inside the package. In experiment, aging time of EMC were varied from 0 to 24 hours for molding process of SOIC-8L packages. For analysis, these packages were tested by x-ray and scanning acoustic microscope to analyze properties of EMC with an aging time and also analyzed delamination, internal void, and wire sweep inside the packages with different aging time. The results revealed that different aging time of EMC effect to properties and reliability performance of molding process.