LDPC Decoder Research Articles

OpenCL/CUDA algorithms for parallel decoding of any irregular LDPC code using GPU

The development of multicore architectures supporting parallel data processing has led to a paradigm shift, which affects communication systems significantly. This article provides a scalable parallel approach of an iterative LDPC decoder, presented in a tutorial-based style. It is suitable for decoding any irregular LDPC code without the limitation of the maximum node degree, and it includes a parallel calculation of the syndrome. This is the main difference from algorithms presented so far. The proposed approach can be implemented in applications supporting massive parallel computing, such as GPU or FPGA devices. The implementation of the LDPC decoder with the use the OpenCL and CUDA frameworks is discussed and the performance evaluation is given at the end of this contribution.

Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders

This brief presents three strategies, including initialization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the number of decoding cycles (DCs) for stochastic low-density parity-check decoding. For the standard IEEE 802.3an code, simulation indicates a 73.6% reduction in the average number of DCs with a satisfactory bit error rate. Moreover, hardware implementation shows that the area required for the proposed decoder is significantly reduced.

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

Nonbinary LDPC codes outperform their binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node (CN) processor, for high-order Galois fields (GFs) higher than GF(16). To overcome this drawback, we propose an approximation for the trellis min–max algorithm that allows us to reduce the number of exchanged messages between the CN and the variable node compared with previous proposals from the literature. On the other hand, we reduce the complexity in the CN processor, keeping the parallel computation of messages. We implemented a layered scheduled decoder, based on this algorithm, in a 90-nm CMOS technology for the (837, 723) NB-LDPC code over GF(32) and the (1536, 1344) over GF(64), achieving an area saving of 16% and 36% for the CN and 10% and 12% for the whole decoder, respectively. The throughput is 1.07 and 1.26 Gb/s, which outperforms the state of the art of high-rate decoders with the high GF order from the literature.

전송효율 향상을 위한 위성 및 수중 통신의 효율적인 융합 모델 연구

In this paper, we analyzed efficient decoding scheme with FTN(Faster than Nyquist) method that is transmission method faster than Nyquist theory and increase the throughput. Applying the FTN method to satellite and underwater communication, we proposed an efficient transceiver model. To minimize ISI(Inter-Symbol Interference) induced by FTN signal, turbo equalization algorithms that iteratively exchange probabilistic information between Viterbi equalizer based on BCJR algorithm and LDPC decoder are used in satellite communication. In others, for underwater communication, DFE equalizer and LDPC decoder are concatenated to improve performance.

Performance of LDPC Decoders With Missing Connections

Due to process variation in nanoscale manufacturing, there may be permanently missing connections in information processing hardware. Due to timing errors in circuits, there may be missed messages in intra-chip communications, equivalent to transiently missing connections. In this work, we investigate the performance of message-passing LDPC decoders in the presence of missing connections. We prove concentration and convergence theorems that validate the use of density evolution performance analysis. Arbitrarily small error probability is not possible with missing connections, but we find suitably defined decoding thresholds for communication systems with binary erasure channels under peeling decoding, as well as binary symmetric channels under Gallager A and B decoding. We see that decoding is robust to missing wires, as decoding thresholds degrade smoothly. Moreover, there is a stochastic facilitation effect in Gallager B decoders with missing connections. We also compare the decoding sensitivity with respect to channel noise and missing wiring.

Low-Complexity First-Two-Minimum-Values Generator for Bit-Serial LDPC Decoding

This brief proposes a low-complexity first-two-minimum-values generator for a bit-serial scheme. Since the hardware complexity of generators utilizes a significant portion of the min-sum low-density parity-check decoder, a low-complexity generator is crucially important. To reduce hardware complexity, an existing bit-serial generator that finds only one minimum value instead of two has been proposed; however, it can cause bit error rate (BER) degradation. By contrast, the proposed low-complexity bit-serial generator can find the exact first two minimum values and thus can improve the BER performance. Moreover, the proposed generator does not suffer from any throughput loss since its latency is almost the same as that of the existing generator.

Read and Write Voltage Signal Optimization for Multi-Level-Cell (MLC) NAND Flash Memory

The multi-level-cell (MLC) NAND flash channel exhibits nonstationary behavior over increasing program and erase (PE) cycles and data retention time. In this paper, an optimization scheme for adjusting the read (quantized) and write (verify) voltage levels to adapt to the nonstationary flash channel is presented. Using a model-based approach to represent the flash channel, incorporating the programming noise, random telegraph noise (RTN), data retention noise and cell-to-cell interference as major signal degradation components, the write-voltage levels are optimized by minimizing the channel error probability. Moreover, for selecting the quantization levels for the read-voltage to facilitate soft LDPC decoding, an entropy-based function is introduced by which the voltage erasure regions (error dominating regions) are controlled to produce the lowest bit/frame error probability. The proposed write and read voltage optimization schemes not only minimize the error probability throughout the operational lifetime of flash memory, but also improve the decoding convergence speed. Finally, to minimize the number of read-voltage quantization levels while ensuring LDPC decoder convergence, the extrinsic information transfer (EXIT) analysis is performed over the MLC flash channel.

Fast Converging ADMM-Penalized Algorithm for LDPC Decoding

The alternate direction method of multipliers (ADMM) approach has been recently considered for LDPC decoding. It has been approved to enhance the error rate performance compared with conventional message passing (MP) techniques in both the waterfall and error floor regions at the cost of a higher computation complexity. In this letter, a formulation of the ADMM decoding algorithm with modified computation scheduling is proposed. It increases the error correction performance of the decoding algorithm and reduces the average computation complexity of the decoding process thanks to a faster convergence. Simulation results show that this modified scheduling speeds up the decoding procedure with regards to the ADMM initial formulation while enhancing the error correction performance. This decoding speed-up is further improved when the proposed scheduling is teamed with a recent complexity reduction method detailed in Wei et al.IEEE Commun. Lett., 2015.

Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation

Most of the recently proposed hardware realizations for non-binary low-density parity-check decoders are ASIC oriented as they employ multiplierless computation units. In this article, we present a...

A modified normalized min-sum algorithm for LDPC decoding using order statistics

In this paper, we propose a new modified normalized min-sum algorithm for low-density parity-check decoding. Instead of normalizing the results of the check node renew calculations by a single modification factor, we use two different modification factors to normalize the results of check node renew calculations. One modification factor for the position of the first minimum value and another modification factor for other positions. We obtain two modification factors by theoretical analysis using the theory of order statistics. Simulation results show that the new modified normalized min-sun algorithm achieves better bit error rate performance than normalized min-sun algorithm without adding implementation complexity. Copyright © 2016 John Wiley & Sons, Ltd.

Unified Designs for High Performance LDPC Decoding on GPGPU

Modern GPGPU's have enabled massively parallel computing with programmability that can exploit the highly parallel nature of LDPC decoding. Previous works customized the design on a GPGPU towards specific execution attributes of a particular LDPC decoding matrix. Supporting different LDPC decoding matrices requires either substantial rework on the current program, or a brand new parallel design. This paper proposes two unified designs that can achieve high performance for both regular and irregular LDPC decoding on a GPGPU. The first design introduces a node-based scheme with a versatile translation array mechanism that can efficiently handle the complex data access patterns of different LDPC decoding matrices. The second design proposes an edge-based parallel paradigm that uses more intuitive data layout. More edges than nodes in a Tanner graph also give the edge-based design higher computation parallelism when there are limited concurrent codewords. With the proposed unified designs, designers can be ignorant of the types of LDPC matrices and achieve high performance LDPC decoding. The experiments on a GTX 470 GPGPU have demonstrated up to 134.56x runtime improvement, when compared with designs on a high-end CPU. The maximum throughput can reach 80.25 Mbps. When compared with the previous customized designs, the proposed systematic designs can reach better performance while relieving the effort of customization.

Performance and Complexity Evaluation of Iterative Receiver for Coded MIMO-OFDM Systems

Multiple-input multiple-output (MIMO) technology in combination with channel coding technique is a promising solution for reliable high data rate transmission in future wireless communication systems. However, these technologies pose significant challenges for the design of an iterative receiver. In this paper, an efficient receiver combining soft-input soft-output (SISO) detection based on low-complexity K-Best (LC-K-Best) decoder with various forward error correction codes, namely, LTE turbo decoder and LDPC decoder, is investigated. We first investigate the convergence behaviors of the iterative MIMO receivers to determine the required inner and outer iterations. Consequently, the performance of LC-K-Best based receiver is evaluated in various LTE channel environments and compared with other MIMO detection schemes. Moreover, the computational complexity of the iterative receiver with different channel coding techniques is evaluated and compared with different modulation orders and coding rates. Simulation results show that LC-K-Best based receiver achieves satisfactory performance-complexity trade-offs.

Self-Adaptive Scaled Min-Sum Algorithm for LDPC Decoders Based on Delta-Min

Self-Adaptive Scaled Min-Sum Algorithm for LDPC Decoders Based on Delta-Min

An Efficient Non Binary LDPC Decoder Using Layered Dynamic Scheduling

An Efficient Non Binary LDPC Decoder Using Layered Dynamic Scheduling

Memory trade-offs in layered self-corrected min-sum LDPC decoders

This paper proposes two variants which aim at reducing the memory requirements of the self-corrected min-sum (SCMS) with respect to min-sum (MS). The first improvement--SCMS-V1--eliminates the need for check node messages' signs storage. The second improvement--SCMS-V2--is based on a novel imprecise self-correction rule, which allows the reduction of the erasure bits. We analyze the decoding performance and the hardware cost for the Min-Sum and three variants of the SCMS decoder for two types of regular and irregular LDPC codes, four coding rates, and two message quantizations. The decoding performance analysis indicates that the SCMS-V2 introduces almost no degradation in the error correction capability with respect to the conventional SCMS, while it has an almost 0.5 dB better performance compared to MS. Regarding the implementation analysis, we use an LDPC customizer tool developed by us in order to generate FPGA based LDPC layered architectures with serial AP-LLR processing and multi-codeword decoding support. The synthesis results for Virtex-7 FPGA devices indicate that the SCMS-V2 has similar cost in both BRAM blocks and slices with the Min-Sum decoder and up to 33 % less than SCMS-V1 decoder and up to 40 % less than SCMS decoder.

A high throughput architecture for a low complexity soft-output demapping algorithm

Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

High-Throughput LDPC Decoder on Low-Power Embedded Processors

Real-time efficient implementations of LDPC decoders have long been considered exclusively reachable using dedicated hardware architectures. Attempts to implement LDPC decoders on CPU and GPU devices have lead to high power consumptions as well as high processing latencies that are incompatible with most embedded and mobile transmission systems. In this letter, we propose ARM-based decoders that go from 50 to 100 Mbps while executing 10 layered-decoding iterations. We hereby demonstrate that efficient LDPC decoders can be implemented on a low-power programmable architecture. The proposed decoders are competitive with recent GPU related works. Therefore, software LDPC decoders constitute a response to software defined radio constraints.

Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages

In this brief, a method for compressing the messages between check nodes and variable nodes is proposed. This method is named compressed nonbinary message passing (CNBMP). CNBMP reduces the number of messages exchanged between one check node and the connected variable nodes from $d_{c} \times q$ to $5 \times q$ , and its application has a high impact on the performance of the decoder: the storage and routing areas are reduced and the throughput is increased. Unlike other methods, CNBMP does not introduce any approximation or modification in the information and the processed operations are exactly the same as those of the original decoders; hence, no performance degradation is introduced. To demonstrate its advantages, an architecture applying this CNBMP to the Trellis Min-Max algorithm was derived showing that most of the storage resources were also reduced from $d_{c} \times q$ to $5 \times q$ . This architecture was implemented for a (837 726) nonbinary low-density parity-check code using a 90-nm CMOS technology reaching a throughput of 981 Mb/s with an area of 10.67 mm2, which is 3.9 more efficient than the best solution found in the literature.

FPGA implementation of low complexity LDPC iterative decoder

ABSTRACTLow-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.

Analysis of Minimal LDPC Decoder System on a Chip Implementation

This paper presents a practical method of po- tential replacement of several different Quasi-Cyclic Low- Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to imple- ment the LDPC encoder and decoder in a memory-con- strained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algo- rithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the pro- posed LDPC setup simplification. Finally, the error per- formance of the modified system structure is evaluated and compared with the original system structure by means of simulation.