LDO Regulator Research Articles

Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs

Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs

과도응답을 향상시킨 피드백 구조를 갖는 LDO 레귤레이터

과도응답을 향상시킨 피드백 구조를 갖는 LDO 레귤레이터

이진 가중치 전류 제어 기법을 이용한 고속 응답 디지털 LDO 레귤레이터

이진 가중치 전류 제어 기법을 이용한 고속 응답 디지털 LDO 레귤레이터

LDO regulator with high power supply rejection at 10 MHz

LDO regulator with high power supply rejection at 10 MHz

병렬 오차 증폭기 구조를 이용하여 과도응답특성을 개선한 On-chip LDO 레귤레이터 설계

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix 0.18 ㎛ CMOS parameters. Chip layout size is 500 ㎛ X 150 ㎛. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

A power management system architecture for LF passive RFID tags

This paper presents a low power, low voltage power management (PM) system for low-frequency passive RFID tags in a standard CMOS 0.18 µm technology. Passive tags have no internal power source but use the incoming RF energy transmitted by a transceiver to power all the circuitry inside them via a rectifier. Due to the wide variation of the rectified voltage as a function of the RF power, two stages of regulation are required: a shunt regulator working as limiter (3 V) at the rectifier output, and a LDO regulator at a tighter range of 1.15 V. Besides that, two blocks monitor the available RF power at the LDO regulated output and flag when the power is low for different tag operation modes: power-on reset during a read event, and power flag during a write event. All blocks rely on a low power resistor-less 3.5 nA current reference and a 400 mV voltage reference. Both references make use of the self cascode MOSFET structure. The complete PM system is functional with 2 µA current.

0.35 ㎛ BCD 공정을 이용한 보호회로 기능이 추가된 모바일용 LDO 레귤레이터

We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and load regulation with load current 0 mA to 40 mA.

A single-event transient hardened LDO regulator with built-in filter

A single-event transient hardened LDO regulator with built-in filter

A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load

A Weighted Current Feedback (WCF) technique for output capacitorless low-dropout (OCL-LDO) regulator is presented in this paper. Through feedback of a weighted current, the WCF permits smart management of the output impedance as well as the gain from the inter-gain stage. Based on the Routh-Hurwitz stability criterion, the WCF can avoid the right-half plane (RHP) pole and push the left-half plane (LHP) non-dominant complex pole pair to a higher frequency. Besides, it provides good regulator loop gain and fast transient response. Validated by UMC 65 nm CMOS process, the simulation and measurement results have shown that the WCF LDO regulator can operate at a load capacitance (C L ) range from 470 pF to 10 nF with only 3.8 pF compensation capacitor. At a supply of 0.75 V and a quiescent current of 15.9 μA, the proposed circuit can support a maximum load current (I L ) of 50 mA. When I L switches from 0 to 50 mA in 100 ns, the output can settle within 400 ns for the whole C L range. For a case of single capacitor (C L 470 pF), the settling time is only 250 ns. The comparison results have shown that the WCF LDO regulator offers a comparable or better transient figure-of-merit (FOM) and additional merit to drive wide load capacitance range.

A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push–Pull Composite Power Transistor

An output-capacitorless low-dropout (OCL-LDO) regulator with a push-pull composite power transistor is presented in this paper. Using the proposed composite transistor, the nondominant parasitic poles can be pushed to higher frequencies, leading to good stability. In addition, the slew rate limitation at the gate of the power transistor is improved greatly by the proposed push-pull structure. Implemented and fabricated in UMC 65-nm CMOS technology, the LDO regulator occupies only an active area of 0.0096 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The experimental results have shown that the regulator is able to operate at VIN = 0.75 V and deliver a maximum load current of 50 mA with a dropout voltage of less than 250 mV. It consumes a quiescent current of 16.2 μA and is able to settle within 1.2 μs.

Design of an Output-Capacitorless LDO Regulator with Adaptive Power Transistors

This paper presents a bandgap reference and an output-capacitorless LDO regulator with adaptive power transistors. The bandgap reference consists of a current reference circuit, a bipolar transistor and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed LDO improves load transient and light load efficiency by permitting the regulator to transform itself between 2-stage and 3-stage topologies, depending on the load current condition. Cadence simulation with SMIC 0.18 μm process shows that the bandgap reference generates a reference voltage 569 mV and the quiescent current is only 0.23 μA, the proposed LDO generates an output voltage 1 V, the quiescent current is 0.88 μA (including bandgap reference) at no-load condition, the undershoot /overshoot voltage is 187 mV/152 mV and the settling time is 5 μs as load current suddenly changes from 0 to 100 mA, or vice versa.

LDO of High Power Supply Rejection with Two-Stage Error Amplifiers and Buffer Compensation

This study develops a low dropout regulator linear regulator, characterized by a high power supply rejection ratio using ultra-low output resistance buffer and two-stage error amplifiers. The high power supply rejection is based on a closed-loop LDO regulator. The ultra-low output resistance buffer achieves ultra-low output impedance with dual shunt feedback loops, subsequently improving load and line regulations, as well as the transient response for low voltage applications. The proposed LDO regulator linear regulator functions under an input voltage of 1.8~3V, and the output voltage can be maintained at around 1.27V. Moreover, its output voltage is independent of input voltage. The proposed regulator is applicable to light-emitting diode driver integrated circuits. The layout chip area of the LDO linear regulator is 21.5μm × 42.6μm.

A FVF LDO Regulator With Dual-Summed Miller Frequency Compensation for Wide Load Capacitance Range Applications

This paper presents a proposed Flipped Voltage Follower (FVF) based output capacitorless low-dropout (OCL-LDO) regulator using Dual-Summed Miller Frequency Compensation (DSMFC) technique. Validated by UMC 65-nm CMOS process, the simulation results have shown that the proposed LDO regulator can be stabilized by a total compensation capacitance (CC) of 8 pF for a load capacitance (CL) ranging from 10 pF to 10 nF. It consumes 23.7 μA quiescent current with a 1.2 V supply voltage. With a dropout voltage of 200 mV, the LDO regulator can support a maximum 50 mA load current. It can settle in less than 1.7 μs with a 1% accuracy for the whole CL range. The proposed LDO regulator is comparable to other reported works in terms of figure-of-merit (FOM). Most significantly, it can drive the widest range of CL and achieve the highest CL(max)/CC ratio with respect to the counterparts.

A High Current Efficiency CMOS LDO Regulator with Low Power Consumption and Small Output Voltage Variation

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is <TEX>$59.2^{\circ}C$</TEX>. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from <TEX>$-40^{\circ}C$</TEX> to <TEX>$125^{\circ}C$</TEX> we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a <TEX>$1{\mu}F$</TEX> output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in <TEX>$0.35{\mu}m$</TEX> CMOS process.

A Sub-1V High-PSRR Piecewise-Linear Bandgap Reference

A piecewise-linear bandagp reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient is designed for analogue and mixed signal systems in this paper. By adopting LDO regulator, the designed high PSRR piecewise-linear BGR achieves well performances and has a simple architecture. Simulation results show that the PSRR of the designed piecewise-linear BGR with LDO regulator at 10Hz, 1kHz and 100kHz achieves, respectively, -110.42dB, -109.18dB and -64.51dB. Compared to the designed BGR without LDO regulator, the PSRR of the designed high PSRR piecewise-linear BGR with LDO regulator has the improvements of about 35dB, 36.9dB and 29.28dB at 10Hz, 1kHz and 100kHz respectively. The designed piecewise-linear BGR with LDO regulator generates an output voltage of 0.68V with 1.65ppm/oC temperature coefficient in the range from -50 oC to 125 oC. The deviation of the output voltage is within 98.23μV when the power supply voltage V DD changes from 1.2V to 7V.

Formal Interpretation of Assertion Based Features on AMS Designs

The paper proposes the adoption of formal methods for modeling of analog functions. It explains how assertions can be overlaid onto the range of values of individual features in an analog function, and proceeds toward building a mathematical (hybrid automata) model to represent and analyze them. An LDO regulator and a battery charger are used as examples.

An Ultra-Low Quiescent Current CMOS Low-Dropout Regulator with Small Output Voltage Variations

An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.

A compact programmable LDO regulator for ultra-low voltage SoC

A compact programmable LDO regulator for ultra-low voltage SoC

A low-voltage high PSR LDO regulator with a simple ripple cancellation technique

A low-voltage high PSR LDO regulator with a simple ripple cancellation technique

UVLO 보호기능이 추가된 LDO 레귤레이터 설계

This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.