Layout Methodology Research Articles

Design and layout of process plants

This study offers a summary of the main consensus professional process plant layout methodology in sufficient detail for it to be used as a template for design activity. This study also deals briefly with the issue of how process plant layout methodology has changed in the last thirty years. It has in summary changed little, other than to the extent that it has been required to do so by tighter regulation of health, safety and environmental matters.

Designing Nelder wheel plots for tree density experiments

The Nelder (Biometrics 18:283–307, 1962) wheel design allows a researcher to test multiple tree densities in a single plot. Because spatial relationships among planted trees are fundamental to a Nelder wheel, a researcher needs a specific set of layout parameters to establish a Nelder plot. While Nelder (Biometrics 18:283–307, 1962) provides calculus-based equations for determining the required layout parameters, the presentation focuses on derivation of these equations and not their application to forestry research. Other authors have outlined the design of Nelder plots for forestry research, but have done so using trigonometry-based equations. Existence of two layout methodologies in the literature is a source of confusion. In this paper, we present a straightforward means to determine the design parameters critical to the establishment of Nelder plots used within tree density research. The layout equations presented are expressed in terms that allow applied forestry researchers to easily answer the following question. Given the number and range of tree densities I want to evaluate, what are the required Nelder wheel layout parameters? Finally, we provide a step-by-step example of the design and installation of a Nelder plot for a scenario familiar to tree density research and discuss analysis of Nelder wheel experiments.

Technology Focus: Health, Safety, and Environment (August 2009)

Technology Focus Health, safety, and environment (HSE) considerations continue to be integral parts of all sectors of the oil and gas industry. The health and safety of the industry work-force as well as of residents in producing regions are of paramount importance to the continued viability of the industry. In a recent example of an international health issue, the April 2009 emergence of a rapidly disseminated strain of swine flu created great concern around the world. Oil and gas industry personnel travel frequently between countries and can contribute to spreading of diseases. Last year I commented on the safety challenges of keeping up with the strong drilling demands resulting from high oil prices. This year offers a new set of challenges. With lower oil prices, companies may have cut back on some activities and programs. Hopefully, safety and environmental programs will remain as important and central elements of everyday work. Industry performance in traditional air- and water-quality and waste-management programs remains very important. Overlain on these are highly visible global issues such as climate change and carbon capture and sequestration. Projects for injecting carbon dioxide into underground formations will need to draw on the decades of expertise in the oil and gas industry. Previously, I have written about the challenges of selecting a small number of top papers to represent three separate disciplines (health, safety, and environment). My own work focuses only on environmental issues. This year, I enlisted the assistance of Tom Knode of Halliburton to help identify the top papers in health, safety, and social responsibility, which are areas within his scope of responsibility. Health, Safety, and Environment additional reading available at OnePetro: www.onepetro.org SPE 121065 • "The Use of Risk Analysis in Design: Safety Aspects Related to the Design and Operation of an FPSO" by Lars Tronstad, SPE, StatoilHydro. SPE 118176 • "Health-Reporting System in the Oil and Gas Business" by Claudio Zappador, Eni, et al. SPE 120973 • "Integrating Social Responsibility Into the Health, Environment, and Safety Management System" by Carolina Ortega Barrales, SPE, Occidental Oil and Gas, et al. SPE 121104 • "Breakthrough Mobile-Water Treatment Converts 75% of Fracturing Flowback Fluid to Fresh Water and Lowers CO2 Emissions" by Aaron D. Horn, SPE, Newfield Exploration. SPE 121050 • "Time To Protect: Layout Methodology for Safe SimOps in High-Pressure, High-Percent-H2S Facilities" by A. Blyth, Shell International.

Study on the general layout of semi-submersible offshore drilling platforms based on process flow

The general layout of 6th generation semi-submersible drilling platforms is the main factor impacting the efficiency of their drilling operations. This paper provides a compound/integrated algorithm based on process flow that is aimed at improving efficiency, while giving attention to stability and safety at the same time. The paper describes the process flow of dual drilling centers and a hierarchical division of rigs based on the different modes of transportation of various drilling support systems. The general layout-centripetal overall arrangement spatially was determined based on drilling efficiency. We derived our modules according to drilling functionality; the modules became our basic layout units. We applied different layout algorithm to mark out the upper and lower decks. That is, the upper deck was designed based on the lowest transportation cost while the lower deck’s calculations were based on the best-fit scope. Storage configurations in columns and pontoons were also considered for the layout design. Finally the center of gravity was taken into consideration and the general layout was adjusted accordingly, to result in an optimal center of gravity. The methodology of the general layout can provide a reference for implementation of domestic designs of semi-submersible rigs.

A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm

Most signals between chips or packages in an electric circuit board require certain delays in order to achieve good timing. An extension of the circuit line that is proportional to the designated time delay has been a usual practice due to cost effectiveness. However, the layout of the line becomes dense due to the small size of packages or circuit boards, and this generates crosstalk, causing signal detection errors. In this paper, a design methodology of delay line layout for crosstalk minimization is developed using the genetic algorithm (GA). The GA requires a large number of function evaluations, and efficient calculation of crosstalk is proposed together with a new technique of generating random line, making offsprings, and mutation. Different optimum results have been obtained for different objectives and compared. Some of the designs were actually manufactured and experimentally tested, showing the validity of the optimum results.

Layout techniques for FPGA switch blocks

This paper presents abstract layout techniques for a variety of field-programmable gate array switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks and good results for large switch blocks. We show how it is possible to transform universal switch blocks into a subset architecture by using the decomposition property of universal switch blocks. This allows universal switch blocks to exploit the same layout methodologies as presented for subset architectures.

Facilities layout planning based on Fuzzy multiple criteria decision-making methodology

Space requirements for facilities and the activity relationships among these facilities are important factors in determining the design of a facility layout. A facility layout problem is an unstructured decision problem. One of the real difficulties in developing and using models for layout design is the natural vagueness associated with the inputs to the models. The personnel flow rate between different departments should be viewed as vague inputs. The analyst is typically uncertain about what this input should be, yet the formulation requires exact inputs. Similarly, arbitrary numerical ratings are assigned for the relationship chart. This paper presents a distinct methodology for the facility layout process using a fuzzy decision-making system for handling inexact, vague data. The selection routine for the placement of facilities (departments) in an open continual plane is developed by using a multifactor fuzzy inference system. It considers both qualitative and quantitative factors that influence the layout structure. A two-tier fuzzy inference system is proposed to compare the proposed layout methodology with that of a conventional selection routine with respect to personnel flow cost, dead space and the minimum required area of the layout. The suggested distinct methodology is coded in C++ language and implemented in a personal computer. The experimental results for a test problem with six departments, 30 activities (moves) and four influencing factors are illustrated with encouraging results under a fuzzy multicriteria environment.

Towards Criteria for Visual Layout of Instructional Multimedia Interfaces

This article investigates the use of 11 refined Gestalt laws as the layout rules for instructional multimedia screen design by way of the redesign of the interface of a multimedia computer application and the subsequent evaluation of this redesigned interface. These layout rules are suitable for designing interfaces for complex learning materials in order to achieve more effective learning environments. To test the usefulness of these layout methodologies in visual screen design, they were applied to the redesign of an instructional multimedia application. Three different user groups evaluated the new screen design by comparing the designs. The evaluation results were overwhelmingly positive. Overall, 85% of the evaluators rated positively both the new design and the value of applying the 11 layout rules to improve the learning. This set of layout rules may also be successfully applied to design many different instructional multimedia applications.

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on di...

Optimization of indoor wireless communication network layouts

Radio Frequency Data Communications (RFDC)technology is rapidly becoming a critical component of many traditional industrial engineering functions including materials tracking, inventory control, warehousing, order processing, shipping and database management. As a means of moving information, RFDC has many attractive features, such as speed, accuracy, reliability, convenience and low operating costs. When implementing RFDC systems a major problem is to quickly and efficiently determine the locations where transceivers should be placed so that effective radio communication can take place. The research described in this paper addresses this issue by developing a computerized layout simulation system that incorporates heuristic optimization methods to solve the placement problem. The effectiveness of this unique automated layout methodology is demonstrated by comparing it with the current method of utilizing manual site surveys, as well as with other placement methods. The methodology and solutions are validated by field-testing at actual facilities.

Enabling alternating phase shifted mask designs for a full logic gate level

The International Technology Roadmap for Semiconductors lists F2 (157 nm exposure wavelength) optical lithography and extreme ultraviolet (EUV) next generation lithography as the two most feasible lithography solutions for the 70 nm technology node. It is very likely that both of these lithography solutions will be late, forcing ArF (193 nm exposure wavelength) lithography to operate at unprecedented resolution levels. Lithographically, alternating phase shifted masks (altPSM) can achieve the resolution required to manufacture 70 nm logic products with ArF lithography equipment [P. Schiavone, F. Lalanne, and A. Prola, Clear field alternating PSM for 193 nm lithography, Proc. SPIE 3679, 582-589 (1999) and M. Fritz et al., Application of chromeless phase-shift masks to sub-100 nm SOI CMOS transistor fabrication, Proc. SPIE 4000, 388-407 (2000)], but technical and logistical challenges associated with the broad implementation of altPSM require novel and invasive EDA solutions which have caused the industry to shy away from altPSM in the past. Since the resolution capabilities of altPSM are well understood in the lithography community, this paper will focus on the challenges facing altPSM implementation for the polysilicon gate level and will present the results of a detailed altPSM design feasibility study done at IBM for the 180 nm technology node. While the 70 nm technology node will push resolution harder then ever before, the design rules, EDA tools, and layout methodologies developed in the past lay the foundation for our attack on this challenging technology node.

Optimization of indoor wireless communication network layouts

Radio Frequency Data Communications (RFDC) technology is rapidly becoming a critical component of many traditional industrial engineering functions including materials tracking, inventory control, warehousing, order processing, shipping and database management. As a means of moving information, RFDC has many attractive features, such as speed, accuracy, reliability, convenience and low operating costs. When implementing RFDC systems a major problem is to quickly and efficiently determine the locations where transceivers should be placed so that effective radio communication can take place. The research described in this paper addresses this issue by developing a computerized layout simulation system that incorporates heuristic optimization methods to solve the placement problem. The effectiveness of this unique automated layout methodology is demonstrated by comparing it with the current method of utilizing manual site surveys, as well as with other placement methods. The methodology and solutions are validated by field-testing at actual facilities.

Modeling and Optimization of End Effector Layout for Handling Compliant Sheet Metal Parts

Material handling of compliant parts is one of the most critical and underresearched problems in the sheet metal stamping industry. The fundamental shortcoming of currently studied material handling systems for sheet metal stamping is the lack of analysis of its impact on part dimensional quality and production throughput. This paper addresses this problem by development of a generic methodology for modeling and optimization of part holding end-effector layout in order to minimize part dimensional deformation during handling operations. The methodology extends the design of “N-2-1” fixturing layout by adding part movability conditions. It considers part CAD model, handling direction and motion kinematic parameters to determine the best end effector layout. This methodology is realized by integrating FEM part and loading modeling with the optimization algorithm. It can be implemented into the design stage of a stamping line so that the trial and error process, which is current industrial practice, can be greatly shortened and the production throughput increased. Experimental results verify the proposed part holding end-effector layout methodology.

A cell-based design approach for RSFQ circuits using a binary decision diagram

We propose a cell-based design approach for rapid single flux quantum (RSFQ) circuits based on a binary decision diagram (BDD). The BDD is a way to represent a logical function using a directed graph which consists of binary switches having one input and two outputs. Since complex logic circuits can be implemented in the form of regular arrays of the BDD binary switches, we can use a cell-based layout methodology for the design of the RSFQ circuits. In this study, we implemented the BDD binary switches by a D2 flip-flop. In the BDD design approach we made a cell library which contains a binary switch, pulse splitters, confluence buffers and Josephson transmission lines. All cell layouts in the library have identical widths and heights, so that any logic function can be laid out by simple connection of the library cells. As a case study, we implemented a 1-bit RSFQ half-adder and a 3-bit encoder for a flash AD converter.

Area-time-power tradeoffs in parallel adders

In this paper, several classes of parallel, synchronous adders are surveyed based on their power, delay and area characteristics. The adders studied include the linear time ripple carry and Manchester carry chain adders, the square-root time carry skip and carry select adders, the logarithmic time carry lookahead adder and its variations, and the constant time signed-digit and carry-save adders. Most of the research in the last few decades has concentrated on reducing the delay of addition. With the rising popularity of portable computers, however, the emphasis is on both high speed and low power operation. In this paper we adopt a uniform static CMOS layout methodology whereby short circuit power mininization is used as the optimization criterion. The relative merits of the different adders are evaluated by performing a detailed transistor-level simulation of the adders using HSPICE. Among the two's complement adders, a variation of the carry lookahead adder, called ELM, was found to have the best power-delay product. Based on the results of our experiments, a large adder design space is formulated from which an architect can choose an adder with the desired characteristics.

VLSI design and implementation of systolic tree queues

A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue.

A study of the use of local interconnect in CMOS leaf cell design

A leaf-cell layout methodology for harnessing the potential of the local interconnect (LI) layer in digital CMOS circuits is presented. Based on the line-of-diffusion layout style, LI is used for selected connections, typically at the output of logic gates, in order to free up the metal-one layer in congested areas. Experimental results based on a variety of logic cells which demonstrate the benefit of the LI in terms of cell area and routing flexibility are presented. Simulation results indicate that this benefit is without any detrimental effect on electrical performance. >

Simulation Modeling in Factory Layout Optimization

This paper presents a new factory layout methodology and its integration in a simulation-based environment for FMS design. Once machines and material handling devices have been selected, a layoutsynthesis tool generates a workscene model used to plan robot trajectories and to investigate material handlingcontrol strategies by means of discrete event simulation. Layouts are represented as orthogonal strctures of loosely packed arrangements of rectangles. They must satisfy a set of qualitative constraints and minimize material handling costs-a function of distances among components. Simulation results are used to modify the input datato thelayout optimization tool, and the layout design process is iterated until a satisfactory solution is reached.

A multi-factor plant layout methodology

Abstract This paper presents a formulation for the plant layout problem, incorporating more than two input factors that may be either qualitative or quantitative in nature. A heuristic is presented which combines a construction and improvement procedure to quickly develop a good layout from the formulation. The output layout from the heuristic may be used directly as the final layout or it may be used as a good starting layout for any other computerized layout improvement procedure. The heuristic is illustrated with a practical example of a large plant with 36 departments.

High speed primitives of hardware accelerators for DSP in GaAs technology

The EUROCHIP initiative is providing foundry, access and full support for a variety of technologies including CMOS and BiCMOS. At present, a GaAs foundry has been selected for high-frequency analogue design (MMIC), and some wafers have been processed. However no foundry runs have yet been selected for GaAs digital circuits. A number of European design laboratories are looking forward to that possibility. Certainly there are not many European foundries with suitable processing. Meanwhile, access to GaAs foundries has been set up by an international university consortium. In particular, this work has been done under the research program in GaAs digital circuits design set up by the Centro de Microelectronica Aplicada, of the University of Las Palmas, in collaboration with the Centre for Gallium Arsenide VLSI Technology, University of Adelaide, and the Middlesex Polytechnic of London. We hope that, in the future, EUROCHIP can support this technology. The paper describes work to design a set of basic computational primitives in digital signal processing (DSP) such as registers, adders and multipliers, and explores the influence of layout and design methodology on the performance of these cells. They have been developed using a design and buffering technique, and symbolic layout notation, well suited for robust design in GaAs DCFL logic. The results obtained so far show that they represent a good compromise between speed, area, and power for VLSI circuits.