Layout Methodology Research Articles

Virtual Plug-In Hybrid Concept Development and Optimization under Real-World Boundary Conditions

The automotive industry faces development challenges due to emerging technologies, regulatory demands, societal trends, and evolving customer mobility needs. These factors contribute to a wide range of vehicle variants and increasingly complex powertrains. The layout of a vehicle is usually based on standardized driving cycles such as WLTC, gradeability, acceleration test cases, and many more. In real-world driving cycles, however, this can lead to limitations under certain boundary conditions. To ensure that all customer requirements are met, vehicle testing is conducted under extreme environmental conditions, e.g., in Sweden or Spain. One way to reduce the development time while ensuring high product quality and cost-effectiveness is to use model-based methods for the comprehensive design of powertrains. This study presents a layout methodology using a top-down approach. Initially, powertrain-relevant requirements for an exemplary target customer are translated into a specification sheet with specific test cases. An overall vehicle model with detailed thermal sub-models is developed to evaluate the different requirements. A baseline design for a C-segment plug-in hybrid vehicle was developed as part of the FVV research project HyFlex-ICE using standardized test cases, highlighting the influence of customer profiles on the design outcome through varying weighting factors. The target customer’s design is analyzed in four real driving scenarios, considering variations in parameters such as the ambient temperature, traffic, driver type, trailer pulling, and battery state-of-charge, to assess their influence on the target variables. In the next step, the potential of hardware technologies and predictive driving functions is examined in selected driving scenarios based on the identified constraints of the baseline design. As a result, four application-specific technology packages (Cost neutral, Cold country, Hot country, and Premium) for different customer requirements and sales markets are defined, which, finally, demonstrates the applicability of the holistic methodology.

A passively self-adjusting floating wind farm layout to increase the energy production: a sensitivity analysis

Offshore wind farm layout design techniques and methodologies currently focus on fixed bottom offshore wind turbines. As more floating wind farm (FWFs) are planned, new methodologies for FWF layout design and optimization are required to consider the different attributes between fixed bottom and floating offshore wind turbines (FOWTs). One main difference is the ability of FOWTs to move in the horizontal plane (surge and sway motions). In our work in [1], we showed that the motions of the FOWTs in the horizontal plane represent an opportunity which can be used to increase the FWF’s annual energy production (AEP). We can passively control the motions of the FOWTs in a FWF according to the incoming wind direction, moving the downwind turbines out of the wake of upwind ones. Since the horizontal motions of a FOWT are governed by the mooring system design (MSD) attached to it, this passive control can be done by designing a customized mooring system (MS) for every FOWT in the farm. In this work we build on our work in [1], as we carry out a sensitivity analysis to check the effect of the farm size and the wind rose on the methodology we introduced. The results show that the percentage increase of energy production due to passively relocating the FOWT is sensitive to the FWF size. Very small FWFs will gain less energy by relocating the FOWTs. Moreover, we show that even with a more uni-directional wind rose relocating the FOWTs in a FWF remains beneficial.

국내 LNG TTS 벙커링 시 안전구역 기준에 관한 연구

This paper suggests an example guideline of a safety zone layout for the domestic LNG Truck-To-Ship (TTS) bunkering. The safety zone is one of the controlled area in LNG bunkering and its layout is required as a fundamental safety barrier. While the international standard provides a layout methodology of the safety zone, its detail application is not user-friendly and only possible with a level of the process engineering. In the domestic case, the enforcement regulations are applied for LNG bunkering but the safety zone is not properly defined for TTS operation. Considerations are made for the intuitive approach of the safety zone layout and an example guideline is suggested for application in the domestic TTS bunkering. A technical background of the guideline is described and its applicability is demonstrated with regard to the characteristics of TTS bunkering. The findings of the study are summarized in association with a practical layout of the safety zone, contributing to the safety culture in the domestic LNG bunkering.

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

Design and Fabrication Approaches of 400–600 V 4H-SiC Lateral MOSFETs for Emerging Power ICs Application

This article reports the demonstration and fabrication of 400-600 V, 4H-SiC lateral MOSFETs on 6-in, N+ substrates. The P-top was implanted on an N- drift region to create a single reduced surface field (RESURF) structure to alleviate the electric field on the surface. The different layout methodologies (source-centered and drain-centered) for making lateral MOSFETs are discussed. The process and design split, such as rapid thermal anneal (RTA) temperatures (900 °C and 1000 °C), different channel designs [accumulation-mode (ACCU) and inversion-mode (INV)], and channel lengths were varied and experimentally analyzed to optimize the device performance. It was confirmed that channel components (channel design and channel length) and RTA temperature are the key ingredients to improve the forward characteristic of the lateral MOSFETs. With the gate to drain length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) of 5 μm, the breakdown voltage of 600 V was achieved with a voltage supporting capability of 120 V/μm. On the other hand, a lateral MOSFET with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> of 2.5 μm and with a further reduced channel length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> = 0.3 μm), a record specific ON-resistance of 7.7 mΩ-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and breakdown voltage of 450 V were achieved. Device design, layout, fabrication, and electrical characteristics of the 400-600 V, 4H-SiC lateral MOSFETs are discussed and reported.

A new cellular manufacturing layout: Multi-floor linear cellular manufacturing layout

The article puts forward the new layout methodology of the multi-floor linear cellular manufacturing layout. The proposed equipment layout methodology not just breaks the conventional single-floor linear cellular manufacturing layout but also meets the layout requirements of the intelligent manufacturing workshop for the stereoscopic aisle manufacturing cell. The layout methodology takes into account the least space occupation as well as the shortest total distance of logistics as the objective function, besides considering the limitations that exist between the equipment, different planes, different levels, and so on; also, a mathematical model is put forward. The multi-floor linear cellular manufacturing layout is solved based on the self-adapting multi-objective fruit fly optimization algorithm that refers to an algorithm combining fruit fly optimization algorithm and NSGA-II. Self-adapting multi-objective fruit fly optimization algorithm makes use of the fast nondominated sorting for the multi-target food concentration calculation, together with designing the adaptive olfactory search and visual search, and employing the perturbation operations for flight strategies, aimed at ensuring the population diversity. Simulation cases suggest that self-adapting multi-objective fruit fly optimization algorithm has stronger advantages as compared with multi-objective fruit fly algorithm and elitist non-dominated sorting genetic algorithm (NSGA-II) in the solution of multi-floor linear cellular manufacturing layout problems. The final engineering case application sheds light on the fact that multi-floor linear cellular manufacturing layout saves 57.6% of the area, in addition to 23.7% of space, and 29.2% of the handling distance as compared with single-floor linear cellular manufacturing layout. Accordingly, multi-floor linear cellular manufacturing layout has a specific reference value in the layout of facilities in the intelligent manufacturing plants.

3-D Layout Optimization of Wind Turbines Considering Fatigue Distribution

As wind resources and land resources become increasingly strained with the rapid expansion of wind energy, the problem of getting a better micro-sitting of wind turbines has gained more and more concerns in the wind industry. A methodology of three-dimension layout of wind turbines (WTs) is proposed in this paper to optimize the horizontal layout and vertical hub height simultaneously. New development of low speed WT technology and influences of micro-sitting of WTs to their O&M costs are considered for the first time. A nested loop consisting of a harmony search algorithm-based layout optimization and a sorting genetic Algorithm-II (NSGA-II)-based turbine selection is also presented to deal with the multi-objective functions. In the optimization process, a polar coordinate transformation-based wake effect model is conducted to simplify the wake effect calculations among the multiwind turbines with different hub height and rotor diameters when the wind direction changes. A 100 MW wind farm case is discussed to illustrate the flexibility and performance improvements of the proposed methodology.

Area-Efficient, 600V 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) for Power Converter Applications

This article reports the demonstration of a low-voltage (<; 600V) monolithically integrated 4H-silicon carbide (SiC) MOSFET and JBS diode (JBSFET). A singlemetal and thermal treatment process were implemented to form ohmic contacts on the n+ and p+ source regions while forming the Schottky contact on the N- SiC epitaxial layer. Different layout methodologies are discussed for fabricating an energy-efficient low-voltage JBSFET by intermittently placing the JBS diode portion in the orthogonal direction to minimize the device area, hence improving the specific ON-resistance and reducing the overall chip size by 46%. A junction termination extension (JTE)-based edge termination structure (the Hybrid-JTE) was implemented to achieve a high breakdown voltage with a very low leakage current. In addition, it was investigated that the forward characteristic of the JBSFET can be further improved by adopting Ti-based metal as the Schottky contact for the JBS diode. Device design, layout approach, fabrication, electrical characterization, and future prospects of the 4H-SiC JBSFETs are discussed in this article.

An Ultralow Phase Noise Eight-Core Fundamental 62-to-67-GHz VCO in 65-nm CMOS

An eight-core fundamental VCO with ultralow phase noise (PN) performance is presented. Eight VCOs are in-phase coupled for low PN, and a 9-dB PN improvement is achieved. A scalable layout methodology is presented to solve the layout difficulties in multicore VCOs. Two VCO cores are connected together directly to form a VCO cell. By simply connecting $N$ /2 VCO cells, the PN of the entire multicore VCO will achieve a 10 logN dB PN improvement compared with the single VCO core. The proposed eight-core VCO is fabricated in 65-nm CMOS and occupies 0.15 mm2. The measured PN is −105.5 dBc/Hz at 1-MHz offset, with the tuning range from 62.2 to 67.3 GHz (7.9%). The VCO consumes 61.2-mW power with the figure-of-merit of −183.5 dBc/Hz at 1-MHz offset.

Development of a Thermally Aware-Compact Model With an Optimized Heat Sink for FinFETs

In this letter, we develop a compact thermal model that can predict changes in the threshold voltage and drain current because of the junction temperature, Δ $T_{J}$ , and its effect on a circuit performance by using circuit simulators. In addition, we propose a thermally aware layout methodology for FinFET-based digital circuits. Although heat sinks (called “via pillars”) are generally used for heat dissipation in FinFETs, these features increase the parasitic capacitance and power consumption. Therefore, we propose an optimized heat sink that is only on the critical node (showing high activity and drain–source voltage, $V_{DS}$ ) and uses high metal stacks up to metal 5. With the optimization of this heat sink, we observe that the $T_{J}$ of a 4-input NAND gate can be reduced about 3.2% while the oscillation frequency of an 11-stage ring oscillator can be increased about 12%, compared to conventional heat sinks.

Adaptive Layout Technique for Microhybrid Integration of Chip-Film Patch

In this paper, a unique adaptive layout methodology for accurate interconnection between two or more functional chips at the wafer level is presented. The methodology is based on an automatic layout modification for each embedded chip with considering exact related offset and rotation after chip embedding. As a result, a wafer-level embedding and accurate interconnecting and integrating of ultrathin chips in the polymer are feasible. The significant application of the presented accurate interconnection between the groups of functional chips is the microhybrid system-in-foil. Also, an adaptive interconnect layout at wafer-level base, allowing for a small wire pitch on and off the chip, leads to reducing silicon area and, thus, saves cost. In this paper, the process flow for embedding and integrating chips based on the adaptive layout technique is presented. The custom designed test chips are processed for the measurement and optimization of overlay accuracy of the adaptive interconnect layout regardless of the chip thickness, warpage, and topography. Besides, the electrical measurements after integrating ultrathin chips in foil confirm the interconnection between chips.

Metodología de distribución de plantas en ambientes de agrupación celular

This article proposes a plant layout methodology for flexible manufacturing systems, based on quantitative methods used to clustering product families, manufacturing cell formation and finally using multicriteria techniques. Fore product clustering, geometric criteria were taken into account and a modified p-median model was used for the formation of cells. Thus, the appropriate layout of facilities was chosen using the Analytic Hierarchy Process, evaluating different alternatives obtained from the Quadratic Assignment Problem model, which takes into account the desired number of cells to be created and the similarity coefficients used for cell clustering. The proposed methodology was tested through an actual case, being verified the suitability of the procedure in a Colombian company from the metalworking sector.

New mass optimization technique to achieve low mass BIW designs using optimal material layout methodology on the frontal vehicle crash

BIW is the car body made of sheet metals welded together. Numerous researches were performed across the world to optimize and save mass on the car body design. This paper describes the new methodology which can be used to reduce mass of the BIW in a full frontal rigid wall impact crash model. The new methodology of identifying materials for the BIW components has been presented. Frontal crash load case has been considered for the research. Since Frontal impact is an evaluation to predict only the frontal performance, parts in the front impact load path like dash, A-pillar, reinforcements and hinge pillar region has been considered as the design space for the material layout optimization. List of materials have been provided as a variable for a list of parts in the BIW and DOE sampling were generated. Response for the DOE designs results have been extracted to study the sensitivity of the parts for the frontal load case and design performance was analysed. Subsequent multi-objective optimization have been performed based on the DOE results, to achieve an optimal material selection for each of the parts in the design space. Further performance improving techniques considering the sensitivity chart have been explored and optimal design with low mass and improved frontal crash performance have been achieved and presented. The use of this methodology on a full vehicle crash model has achieved 15.4 % mass saving with the performance better than the baseline design.

Novel electromagnetic bandgap structure to mitigate simultaneous switching noise for mixed-signal system applications

This paper proposes a novel T-shape electromagnetic bandgap (EBG) structure to suppress simultaneous switching noise (SSN) in mixed-signal systems. Noise is generated due to simultaneous switching multiple drivers in the digital ICs. It is called as SSN. It could propagate between power and ground planes of underlying PCB platform and interfere with the functionality of nearby RF/Analog ICs. So, the RF modules are isolated from the digital module for proper functioning of entire mixed-signal system. A high-impedance surface, called T-shape EBG has been implemented between digital and RF modules. It will exhibit the characteristics of bandgap for a wide frequency range to suppress the propagation of switching noise. A single unit-cell of T-EBG is periodically patterned over one side of the PCB and the other side is kept continuous. In this paper different characteristics of T-EBG have been simulated and verified with the measurement results. A 3 × 3 T-EBG layout provides an isolation of −40 dB from 0.72 to 6.39 GHz. A scaled version of T-EBG is used to shift the bandgap towards higher frequency range from 2.22 to 7.19 GHz. Also, a novel layout methodology has been proposed to broaden the bandgap from 2.02 to 18.84 GHz without reducing the thickness of dielectric substrate.

Sources of Experimental Variation in 2-D Maps: The Importance of Experimental Design in Gel-Based Proteomics.

The success of proteomic studies employing 2-D maps largely depends on the way surveys and experiments have been organized and performed. Planning gel-based proteomic experiments involves the selection of equipment, methodology, treatments, types and number of samples, experimental layout, and methods for data analysis. A good experimental design will maximize the output of the experiment while taking into account the biological and technical resources available. In this chapter we provide guidelines to assist proteomics researchers in all these choices and help them to design quantitative 2-DE experiments.

A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving

This paper presents an energy-recycling micro-architecture and the associated adiabatic logic for ultra-low energy applications, such as implantable bioelectronics. The proposed design achieves low power by transferring and recycling energy between digital logic blocks along with the signal propagation. The CMOS-like layout methodology allows the adiabatic logic core to be synthesized and auto-placed-and-routed with current EDA tools for complex digital systems. A 50% energy saving can be achieved for up to 100 MHz compared to conventional static CMOS logic. As a proof of concept, a 14-tap 8-bit finite impulse response (FIR) filter has been implemented in 90-nm CMOS for implantable neural signal processing. With only 16% area overhead compared to the static CMOS counterpart, the proposed design achieves 70% to 53% of energy reduction for 87 kHz to 410 kHz from a 1 V supply. The FIR filter realized with the proposed energy-recycling logic achieves an FoM of 5.33 nW/MHz/Tap/In-bit/Coeff-bit, yielding a 1.9 $\times$ to 42 $\times$ higher energy efficiency than the state-of-the-art custom energy-efficient FIR designs.

Heliostat field layout methodology in central receiver systems based on efficiency-related distribution

This paper deals with a methodology for heliostat field layout. The methodology, described and validated herein, includes a detailed calculation model for the heliostat field’s mean annual optical efficiency covering the factors of cosine efficiency, shading and blocking efficiency, mirror reflectivity, atmospheric attenuation and receiver interception efficiency. Certain measures are taken to reduce the time consumption for the calculation of the shading and blocking efficiency. On the basis of the performance calculation model the field generation methodology, in which the heliostat field is generated by means of adding the heliostats to the field in sequence, is proposed. This new methodology does not yet perform a grand optimization and it currently depends on the running of other codes to determine optimum tower height and receiver dimensions. In this described methodology, the annually equivalent efficiency distribution (AEED), in pursuit of the maximization of the field’s efficiency, is first proposed and calculated as the basis of positioning the heliostats. Not only the shadowing and blocking effects of the existing heliostats, but also the effects of the heliostats added to the existing heliostats are considered in AEED. The newly added heliostat should be positioned on the best position of the updated AEED so that the average efficiency of the existent heliostats including that new heliostat reaches a maximum. The PS10 field is rearranged by using the AEED-based method and the result shows that the rearranged field improves the original PS10 field by 0.57% in the mean annual optical efficiency and 1.19% in the insolation unweighted efficiency. Furthermore, on the basis of the above method, the cost is taken into account and the efficiency/cost ratio distribution (ECRD) is then used for field generation. The rearrangement result suggests that ECRD-based field has substantially reduced the land area of AEED-based field and shown a good performance in the levelized energy cost.

FORMALIZED PROJECT METHODOLOGY OF EFFECTIVE LAYOUT PLANNING FOR INNOVATIVE UNIVERSITY

The article deals with the university’s effective use of its premises as part of the concept of exercising ownership powers by Ministry of Education and Science of the Russian Federation in relation to property of its affiliates. To solve this problem, the applicability of formalized project methodology of effective layout planning for innovative university is analyzed.

Research on Problems of Logistics Park Layout Optimization Based on Low-Carbon Concept

Around the goal of building a low-carbon logistics park, three aspects about layout optimization related issues which are functional area layout, warehouse layout and road layout are mainly studied in this paper. Functional areas dividing and layout methodology of a low-carbon logistics park are proposed in this paper. Summarizes common methods and main considerations of warehouse layout on the basis of warehouse operation process. Finally proposes methods of road network layout and optimizations of the layout according to the division of different levels of road network in logistics park.

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first-order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and cooptimize design rules, patterning technologies, layout methodologies, and library architectures.