Development of a Thermally Aware-Compact Model With an Optimized Heat Sink for FinFETs

Abstract

In this letter, we develop a compact thermal model that can predict changes in the threshold voltage and drain current because of the junction temperature, Δ $T_{J}$ , and its effect on a circuit performance by using circuit simulators. In addition, we propose a thermally aware layout methodology for FinFET-based digital circuits. Although heat sinks (called “via pillars”) are generally used for heat dissipation in FinFETs, these features increase the parasitic capacitance and power consumption. Therefore, we propose an optimized heat sink that is only on the critical node (showing high activity and drain–source voltage, $V_{DS}$ ) and uses high metal stacks up to metal 5. With the optimization of this heat sink, we observe that the $T_{J}$ of a 4-input NAND gate can be reduced about 3.2% while the oscillation frequency of an 11-stage ring oscillator can be increased about 12%, compared to conventional heat sinks.