Layout Density Research Articles

Apply Plant Fiber to Enrich the Microorganism for Degrading the Polycyclic Aromatic Hydrocarbons in Water

Application of brown hair fiber, ramie fiber, jute fiber and flax fiber to degrade PAHs in water was studied. The experimental results show that the plant fibers which enrich the microbial has better effect of degradation on PAHs in water,and the degradation effects are highly related with plant fiber’s layout density,HRT and aeration rate. The higher the layout density of jute fiver,HRT and aeration rate,the better the effects of decontamination,which means the water quality of effluent meets the GB5749-2006 standard that the total content of PAHs is less than 2000 ng•L-1. Select No11~No14 Tank plant fiber density,6h HRT and 12h aeration,the effect of degradation of PAHs is the best. This result shows that microbial enriched by plant fiber has a good effect of degrading PAHs in water. Plant fibers provide a space as large as possible for indigenous bacteria attached to the growth in water,and also provide a good micro-environment for their biochemical reaction. The indigenous microorganisms attached to the surface of plant fibers rapidly grow to achieve strengthen the natural degradation of the PAHs in water. Except the biodegradable role of plant fiber enrich the microorganisms to degrade PAHs,in addition,there also exists absorption and evaporation effects. Macrocyclic PAHs ring has a more strong hydrophobicity than the small ring,so that in the process of biodegradation,the small ring is more easily to be absorbed by the plant fiber and biofilm surface,and more easily to be degraded. Therefore,plant fiber enriched microbial to degrade PAHs is the main process,then followed by adsorption and evaporation process.

Study of Low Detonation Velocity Explosives Used in Explosion Welding

In order to solve a series of questions on low detonation velocity explosives used in explosion welding which was added into lots of salt, for example hand mixing is heterogeneous, low velocity detonation is unstable, moisture absorption and agglomeration of explosive is easy, ammonium nitrate (AN), wax, diluent, surfactant, gelling agent were mixed into slurry liquid when water temperature was controlled within 105-115°C, and after this liquid was dried, sieved, and cooled at the pressure between -0.07and -0.09Mpa, it can made low detonation velocity explosives used in explosion welding. The microstructure and moisture absorption of the explosive was analyzed, the influence of the charge layout density and thickness on detonation velocity was researched. The results show that each component of the explosives is homogeneous, and is not easy to absorb moisture. When the density is 0.71-0.74g﹒cm-3, the detonation velocity is 2300-2380m﹒s-1,which can satisfy the requirement of explosion welding of mental plate.

Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells

In this paper, issues related to the physical design and layout density of FinFET standard cells are discussed. Analysis significantly extends previous analyses, which considered the simplistic case of a single FinFET device or extremely simple circuits. Results show that analysis of a single device cannot predict the layout density of FinFET cells, due to the additional spacing constraints imposed by the standard cell structure. Results on the layout density of FinFET standard cell circuits are derived by building and analyzing various cell libraries in 32-nm technology, based on three-terminal (3T) and four-terminal (4T) devices, as well as on the recently proposed cells with mixed 3T-4T devices (MT). The results obtained for spacer- and lithography-defined FinFETs are observed from the technology scaling perspective by also considering 45- and 65-nm libraries. The effect of the fin and cell height on the layout density is studied. Results show that 3T and MT FinFET standard cells can have the same layout density as bulk cells (or better) for low (moderate) fin heights. Instead, 4T standard cells have an unacceptably worse layout density. Hence, MT standard cells turn out to be the only viable option to apply back biasing in FinFET standard cell circuits.

Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill

To reduce chip-scale topography variation in chemical mechanical polishing process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated the density-driven dummy fill problem as a standard linear program (LP). However, solving the huge linear program formed by real-life designs is very expensive and has become the hurdle in deploying the technology. Even though there exist efficient heuristics, their performance cannot be guaranteed. Furthermore, dummy fill can also change the interconnect coupling capacitance which might lead to a significant influence on circuit delay, crosstalk, and power consumption. In this paper, we develop a dummy fill algorithm that can be applied to solve both the traditional density-driven problem and the problem considering fill-induced coupling capacitance impact. The proposed algorithm is both efficient and with provably good performance, which is based on a fully polynomial time approximation scheme by Fleischer for covering LP problems. Moreover, based on the approximation algorithm, we also propose a new greedy iterative algorithm to achieve high quality solutions more efficiently than previous Monte Carlo based heuristic methods. Final experimental results demonstrate the effectiveness and efficiency of our algorithms.

Design for manufacturability: IC layout density optimization by minimum-variance method

Design for manufacturing is important in the deep-submicron regime. Increasing integrated circuit (IC) layout uniformity by adding non-functional metal lines in the empty area, so-called dummy feature filling, is an efficient and effective way to reduce pattern-induced topography variation in the chemical–mechanical polishing (CMP) process of IC fabrication. Most existing dummy feature filling methods for IC layout density optimization seek to minimize the effective density range (ρ H− ρ L), where ρ H is the highest and ρ L is the lowest effective density calculated by CMP models. This objective function is not suitable for designs with a wide pattern-density range. First, the minimum value of the effective density range (ρ H− ρ L) may be fixed because ρ L or ρ H is constrained by chip design and, second, all effective densities will be brought as close as possible to ρ H, making the final effective density distribution inappropriate for process recipe development. Here, we propose a new objective function–minimize the overall effective density variance . This overcomes the limitations of existing minimum-range approaches. Because linear programming methods for solving minimum-variance problems are time consuming, a mean-based heuristic method is proposed with reduced computational cost. Experiments on two large-sized IC designs showed that the proposed minimum-variance dummy filling method not only achieved the minimum effective density range, but also minimized the effective density variance of the designed layouts.

A Novel Approach to Analyze and Model Feature Size Effects in CMP

In order to characterize and model the pitch dependency of the step-height decay in a typical oxide CMP process, we measured surface profiles for line-space patterns at 50% density but different pitches. The profiles are analyzed in the spatial frequency domain. For long polishing times, we find a linear dependency between the exponential decay rate and the spatial frequency. From this observation, we derive a simple mathematical model to calculate the post-CMP topography based on the layout density. Application to a typical DRAM metalization layer shows remarkably good qualitative agreement with an error in the predicted heights of plusmn15 nm.

Segmentation of historical machine-printed documents using Adaptive Run Length Smoothing and skeleton segmentation paths

In this paper, we strive towards the development of efficient techniques in order to segment document pages resulting from the digitization of historical machine-printed sources. This kind of documents often suffer from low quality and local skew, several degradations due to the old printing matrix quality or ink diffusion, and exhibit complex and dense layout. To face these problems, we introduce the following innovative aspects: (i) use of a novel Adaptive Run Length Smoothing Algorithm (ARLSA) in order to face the problem of complex and dense document layout, (ii) detection of noisy areas and punctuation marks that are usual in historical machine-printed documents, (iii) detection of possible obstacles formed from background areas in order to separate neighboring text columns or text lines, and (iv) use of skeleton segmentation paths in order to isolate possible connected characters. Comparative experiments using several historical machine-printed documents prove the efficiency of the proposed technique.

Uncluttering Graph Layouts Using Anisotropic Diffusion and Mass Transport

Many graph layouts include very dense areas, making the layout difficult to understand. In this paper, we propose a technique for modifying an existing layout in order to reduce the clutter in dense areas. A physically inspired evolution process based on a modified heat equation is used to create an improved layout density image, making better use of available screen space. Using results from optimal mass transport problems, a warp to the improved density image is computed. The graph nodes are displaced according to the warp. The warp maintains the overall structure of the graph, thus limiting disturbances to the mental map, while reducing the clutter in dense areas of the layout. The complexity of the algorithm depends mainly on the resolution of the image visualizing the graph and is linear in the size of the graph. This allows scaling the computation according to required running times. It is demonstrated how the algorithm can be significantly accelerated using a graphics processing unit (GPU), resulting in the ability to handle large graphs in a matter of seconds. Results on several layout algorithms and applications are demonstrated.

Simulation of the sub-melt laser anneal process in 45 CMOS technology—Application to the thermal pattern effects

Due to the continuous CMOS transistor scaling requirements, sub-melt millisecond laser annealing has been introduced in 45 nm CMOS technology to enhance dopant activation without any additional diffusion. Because of the design, the device layout at the wafer surface introduces during this process significant variations of optical absorption and heat transfer that can induce temperature non-uniformities over the die, detrimental to the device and often called “pattern effects”. The introduction of an absorbent layer above the wafer reduces the optical properties dispersion, but the temperature variations generated by the thermal properties non-homogeneities cannot be suppressed. The impossibility to measure directly this local transient temperature effects on complex transistors layout requires simulation. A thermal simulation has been developed and calibrated to model with accuracy the laser annealing with the real process parameters. This model is used to obtain the transient temperature distribution over the devices, which is needed to understand the laser impact on the transistors performance. We demonstrate that the shallow trench isolation (STI) filled with silicon oxide is critical for these thermal pattern effects. Depending on the STI layout density, temperature variations up to 50 °C over a die are observed.

Accurate Modeling Method for Cu Interconnect

This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully, incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15μm CMOS using this method and confirmed that 10%τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90nm, 65nm and 55nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

Simplified Macromodel of MTLs With Incident Fields (SiMMIF)

Electromagnetic compatibility (EMC) analysis of high-speed designs has become imperative due to rapidly increasing radio-frequency interference and emerging technological trends such as higher operating frequencies, denser layouts, and multifunction convergent products. In this paper, a simplified macromodel of multiconductor transmission lines (MTLs) exposed to incident fields is presented. The proposed formulation can also handle frequency dependence of resistance, capacitance, conductance, and inductance (RLGC) line parameters. The method employs the recently developed delay-extraction-based compact and passive MTL macromodel, while developing closed-form expressions for incident field analysis. An error bound for the proposed macromodel is also presented. The macromodel is simulation program with integrated circuit emphasis (SPICE) compatible and overcomes the mixed frequency/time simulation difficulties usually encountered during transient analysis, while guaranteeing the stability of the global transient simulation. The algorithm provides higher accuracy as well as significant speed gains for EMC analysis of transmission line networks as compared to the existing techniques.

606 クラシックギターの表面板力木等配置の変更の効果について

In the research of the tone quality of a classic guitar, the control of the vibration modes on the surface board is important. It is necessary to combine the traditional trial and error approach with the engineering approach. Here are the some kinds of studies for stiffening rib layout on the sound board of the guitar. We need to get the impact volume of the guitar sound for the lower frequency zone and the rich quality of the sound for the higher frequency zone. We give the suitable distribution of stiffening rib layout density for the optimization of the guitar sound.

High-Efficiency Green Function-Based Thermal Simulation Algorithms

Due to technology scaling trends, the accurate and efficient calculations of the temperature distribution corresponding to a specific circuit layout and power density distribution will become indispensable in the design of high-performance very large scale integrated circuits. In this paper, we present three highly efficient thermal simulation algorithms for calculating the on-chip temperature distribution in a multilayered substrate structure. All three algorithms are based on the concept of the Green function and utilize the technique of discrete cosine transform. However, the application areas of the algorithms are different. The first algorithm is suitable for localized analysis in thermal problems, whereas the second algorithm targets full-chip temperature profiling. The third algorithm, which combines the advantages of the first two algorithms, can be used to perform thermal simulations where the accuracy requirement differs from place to place over the same chip. Experimental results show that all three algorithms can achieve relative errors of around 1% compared with that of a commercial computational fluid dynamic software package for thermal analysis, whereas their efficiencies are orders of magnitude higher than that of the direct application of the Green function method.

Design and Characterization of the EBG Waveguide-Based Interconnects

An alternative signal guiding structure, which can be integrated within the printed circuit substrates, is investigated in this paper. The structure is realized by forming a rectangular waveguide in a 2-D electromagnetic bandgap (EBG) substrate. In this manner, a bandpass interconnect is provided that proves to be a promising technology for the high-speed/high-frequency system design. A systematic approach to the design and optimization of this interconnect is presented here followed by investigation of various bend geometries. The studied structures exhibit very low levels of loss and leakage when inspected at tens of gigahertz frequency range. Moreover, the near-end and the far-end crosstalks are monitored in multiple interconnects proving the high efficiency of this alternative routing structure in dense layouts. Nonetheless, the crosstalk performance is degraded as the coplanar microstrip-to-waveguide transitions are added. These transitions are essentially tapered microstrip lines that are connected to other circuitries. Continuous via fences are inserted in the transition sections of multiple structures demonstrating significant improvement in the crosstalk performance.

An Area and Power Efficient Radiation Hardened by Design Flip-Flop

A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latch master and DICE slave are used. Two shift register chains each comprised of 1920 flip-flops have been implemented in the IBM 0.13 mum bulk CMOS process. Measured SEE immunity in accelerated heavy ion testing, and power results are described. A threshold LET over 45 LET (MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> /mg) at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1.5 V is demonstrated. High layout density and the likely high LET failure mechanisms are described

TreePlus: Interactive Exploration of Networks with Enhanced Tree Layouts

Despite extensive research, it is still difficult to produce effective interactive layouts for large graphs. Dense layout and occlusion make food webs, ontologies, and social networks difficult to understand and interact with. We propose a new interactive Visual Analytics component called TreePlus that is based on a tree-style layout. TreePlus reveals the missing graph structure with visualization and interaction while maintaining good readability. To support exploration of the local structure of the graph and gathering of information from the extensive reading of labels, we use a guiding metaphor of "Plant a seed and watch it grow." It allows users to start with a node and expand the graph as needed, which complements the classic overview techniques that can be effective at (but often limited to) revealing clusters. We describe our design goals, describe the interface, and report on a controlled user study with 28 participants comparing TreePlus with a traditional graph interface for six tasks. In general, the advantage of TreePlus over the traditional interface increased as the density of the displayed data increased. Participants also reported higher levels of confidence in their answers with TreePlus and most of them preferred TreePlus.

Analysis of noise coupling from a power distribution network to signal traces in high-speed multilayer printed circuit boards

As layout density increases in highly integrated multilayer printed circuit boards (PCBs), the noise that exists in the power distribution network (PDN) is increasingly coupled to the signal traces, and precise modeling to describe the coupling phenomenon becomes necessary. This paper presents a model to describe noise coupling between the power/ground planes and signal traces in multilayer systems. An analytical model for the coupling has been successfully derived, and the coupling mechanism was rigorously analyzed and clarified. Wave equations for a signal trace with power/ground noise were solved by imposing boundary conditions. Measurements in both the frequency and time domains have been conducted to confirm the validity of the proposed model.

64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS

This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25 GHz clock frequency and its power/maximal frequency ratio is 151.4 μW/MHz.

Use of optical defocus components to investigate and improve pattern spatial frequency characteristics for more robust layouts

As semiconductor manufacturing moves to smaller geometries, the existing methodologies for verifying the manufacturability of a design are increasingly cumbersome. Current practice is to use geometric “design rules”—such as minimum spacing and width constraints—to identify design configurations that are not manufacturable or likely to reduce yield. One manufacturing property that is particularly difficult to capture accurately with geometric rules is the robustness of the layout configuration with respect to variation through the lithographic process window. The nonlinear characteristics of optical partial coherence effects, particularly strong in modern exposure systems with off-axis illumination, are currently incorporated into the design rules through an exhaustive empirical process. The resulting design rules can be overly conservative to insure complete problem pattern capture, and this may result in unnecessary restrictions on the design that reduce the layout density or interfere with circuit performance. In this article a process model that has been designed to identify process sensitive layout configurations is presented. The model is a spatial filter constructed to select the diffraction components that are most sensitive to focus variation. This defocus model then may be applied to a layout pattern to find features that suffer with lithography focus variation. In addition, the technique may be employed once the optical components of a manufacturing process have been developed. Current results show a good correlation between patterns highlighted using the defocus filter and patterns which will be sensitive to process variations during simulated manufacturing. It is believed that this methodology integrated into physical verification techniques will help to identify yield-limiting layout configurations.

AlGaN/GaN Power HFET on Silicon Substrate With Source-Via Grounding (SVG) Structure

We have developed a high-power AlGaN/GaN HFET fabricated on 4-in conductive Si substrate with a source-via grounding (SVG) structure. The SVG structure enables efficient chip layout and high packing density by the vertical configuration. By establishing a high-quality epitaxial technology on a Si substrate and by significantly reducing the parasitic resistance, a very low specific on-state resistance of 1.9 m/spl Omega//spl middot/cm/sup 2/ is achieved. The breakdown voltage is as high as 350 V, which is attributed to the Si substrate acting as a backside field plate. Because of reduction of the parasitic inductance, very high level of current (2.0 kA/cm/sup 2/) transients, i.e., a turn-on time of 98 ps and a turn-off time of 96 ps, are successfully measured for the first time.