Circuit Layer Research Articles

Ion-native variational ansatz for quantum approximate optimization

Variational quantum algorithms involve training parameterized quantum circuits using a classical co-processor. An important variational algorithm, designed for combinatorial optimization, is the quantum approximate optimization algorithm. Realization of this algorithm on any modern quantum processor requires either embedding a problem instance into a Hamiltonian or emulating the corresponding propagator by a gate sequence. For a vast range of problem instances this is impossible due to current circuit depth and hardware limitations. Hence we adapt the variational approach -- using ion native Hamiltonians -- to create ansatze families that can prepare the ground states of more general problem Hamiltonians. We analytically determine symmetry protected classes that make certain problem instances inaccessible unless this symmetry is broken. We exhaustively search over six qubits and consider upto twenty circuit layers, demonstrating that symmetry can be broken to solve all problem instances of the Sherrington-Kirkpatrick Hamiltonian. Going further, we numerically demonstrate training convergence and level-wise improvement for up to twenty qubits. Specifically these findings widen the class problem instances which might be solved by ion based quantum processors. Generally these results serve as a test-bed for quantum approximate optimization approaches based on system native Hamiltonians and symmetry protection.

Scaling quantum approximate optimization on near-term hardware

The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.

Fully Inkjet-Printed Chemiresistive Sensor Array Based on Molecularly Imprinted Sol-Gel Active Materials.

The fabrication of chemiresistive sensors by inkjet printing is recognized as a breakthrough in gas-sensing applications. One challenge of this technology, however, is how to enhance the cross-selectivity of the sensor array. Herein, we present a ketjen black (KB) ink and molecularly imprinted sol-gel (MISG) inks to support the fabrication of a fully inkjet-printed chemiresistive sensor array, enabling the highly accurate recognition of volatile organic acids (VOAs) on the molecular level. The MISG/KB sensor array was prepared on a glossy photographic paper with a three-layer structure: a circuit layer by a commercial silver ink, a conductive layer by a KB ink, and an active selective layer by MISG inks imprinted by different templates. Hexanoic acid (HA), heptanoic acid, and octanoic acid were used as templates to prepare the MISGs and as targets to evaluate the detection and discrimination performance of the sensor array. Three resultant MISG/KB sensors exhibited high sensitivity and selectivity to VOA vapors. The limit of detection and imprinting factor were 0.018 ppm and 7.82, respectively, for HA-MISG/KB sensors to the corresponding target. With linear discriminant analysis of the gas responses, the MISG/KB sensor array can realize high discrimination to VOAs in single and binary mixtures. Furthermore, the proposed sensor array showed strong sensor robustness with excellent consistency, durability, bending, and humidity resistance. This work developed a fully inkjet-printed chemiresistive sensor array, enabling the realization of high cross-selectivity detection, achieving low-cost, scalable, and highly reproducible sensor fabrication, moving it closer to reliable, commercial, and wearable multi-analyte human body odor analysis potential.

Dual-Layer Slow-Wave Half-Mode Substrate Integrated Waveguide E-Plane Coupler

In this brief, an ultra-compact broad wall coupler based on slow-wave half-mode substrate integrated waveguide (SW-HMSIW) is presented. The E-plane coupling between different layers of circuits under slow-wave effect is studied for the first time. The slow-wave construction is realized by complementary split ring resonator (CSRR) loaded HMSIW. Moreover, CSRRs could serve as coupling sections at the same time. Hence, the slow-wave effect and energy coupling can support each other and operate well together simultaneously. Furthermore, the slow-wave effect could enhance the coupling level of each aperture and realize coupler size reduction in general. As a result, the presented coupler can operate in a wide band (45%) with 50% size reduction comparing to typical HMSIW fast-wave one, which would be suitable for applications in six-port circuit and Butler matrix with strict size and performance requirements. Simulated results are in good agreement with measured data.

Robust System Design IEEE IOLTS 2021

You are reading the Editorial of the Special Section of IEEE Transactions on Device and Materials Reliability with a collection of the best papers of the 2021 (27^th) edition of IEEE IOLTS, an established IEEE symposium which focuses on all critical challenges and important solutions for computing and electronic circuits and systems <i>robust design</i>. Robustness from the IOLTS technical point of view spans across the technology, circuit, microarchitecture, architecture, system, and software layers.

Interface Instability of Integrated Circuit Layers under Electric Current and Mechanical Stress

Interface Instability of Integrated Circuit Layers under Electric Current and Mechanical Stress

Fixed Point Attractor Theory Bridges Structure and Function in C. elegans Neuronal Network.

Understanding the structure–function relationship in a neuronal network is one of the major challenges in neuroscience research. Despite increasing researches at circuit connectivity and neural network structure, their structure-based biological interpretability remains unclear. Based on the attractor theory, here we develop an analytical framework that links neural circuit structures and their functions together through fixed point attractor in Caenorhabditis elegans. In this framework, we successfully established the structural condition for the emergence of multiple fixed points in C. elegans connectome. Then we construct a finite state machine to explain how functions related to bistable phenomena at the neural activity and behavioral levels are encoded. By applying the proposed framework to the command circuit in C. elegans, we provide a circuit level interpretation for the forward-reverse switching behaviors. Interestingly, network properties of the command circuit and first layer amphid interneuron circuit can also be inferred from their functions in this framework. Our research indicates the reliability of the fixed point attractor bridging circuit structure and functions, suggesting its potential applicability to more complex neuronal circuits in other species.

Automotive optoelectronic components submitted to thermal shock: Impact of component architecture on mechanical reliability

New LED technologies & modules allow glare-free automotive lighting. Valeo solutions include the first high-definition LED lighting system. These LEDs technology endure extreme tests conditions in form of thermal shocks or mechanical vibrations to insure reliability under the lifetime of automotive usage. Strict regulations require lead-free solders. Advanced optimization of LEDs for automotive lighting led to multilayered and miniaturized stack-ups. The first lead-free solders were revealed as a weak part of the electronic components and LED assembly. Enormous efforts have been spent on optimizing the lead-free solder material, design and reflow process. However, component miniaturization can also lead to high thermal gradients. Present work analyses the relation between component architectures and thermal shock induced fatigue damage. First, damage after N1 and N2 thermal shock cycles was characterized experimentally. Genuine sample preparations by a Cross polisher followed by high-resolution SEM observations reveal void growth in the solder material and cracking in the current circuit Layer. A two-scale finite element model reproduces both damage types. Simulation results can help to provide design improvements on the component architectures and modules to avoid (minimize) both damage types.

Analyzing the performance of variational quantum factoring on a superconducting quantum processor

In the near-term, hybrid quantum-classical algorithms hold great potential for outperforming classical approaches. Understanding how these two computing paradigms work in tandem is critical for identifying areas where such hybrid algorithms could provide a quantum advantage. In this work, we study a QAOA-based quantum optimization approach by implementing the Variational Quantum Factoring (VQF) algorithm. We execute experimental demonstrations using a superconducting quantum processor, and investigate the trade off between quantum resources (number of qubits and circuit depth) and the probability that a given biprime is successfully factored. In our experiments, the integers 1099551473989, 3127, and 6557 are factored with 3, 4, and 5 qubits, respectively, using a QAOA ansatz with up to 8 layers and we are able to identify the optimal number of circuit layers for a given instance to maximize success probability. Furthermore, we demonstrate the impact of different noise sources on the performance of QAOA, and reveal the coherent error caused by the residual ZZ-coupling between qubits as a dominant source of error in a near-term superconducting quantum processor.

Backscatter Communications

This paper addresses backscatter communications as a new paradigm for Internet of Things (IoT) sensor wireless solutions. The paper clearly presents the history background of the technology and then makes a summary of the more recent developments form several groups around the world, with emphasis in US and Europe groups. The analysis done in this paper will address circuit and physical layer approaches for such a solution and its real implementations, having in mind IoT sensors for long range high speed communications.

A fuzzy hierarchical reinforcement learning based scheduling method for semiconductor wafer manufacturing systems

Scheduling semiconductor wafer manufacturing systems has been viewed as one of the most challenging optimization problems owing to the complicated constraints, and dynamic system environment. This paper proposes a fuzzy hierarchical reinforcement learning (FHRL) approach to schedule a SWFS, which controls the cycle time (CT) of each wafer lot to improve on-time delivery by adjusting the priority of each wafer lot. To cope with the layer correlation and wafer correlation of CT due to the re-entrant process constraint, a hierarchical model is presented with a recurrent reinforcement learning (RL) unit in each layer to control the corresponding sub-CT of each integrated circuit layer. In each RL unit, a fuzzy reward calculator is designed to reduce the impact of uncertainty of expected finishing time caused by the rematching of a lot to a delivery batch. The results demonstrate that the mean deviation (MD) between the actual and expected completion time of wafer lots under the scheduling of the FHRL approach is only about 30 % of the compared methods in the whole SWFS.

Proton radiation hardness of x-ray SOI pixel sensors with pinned depleted diode structure

X-ray silicon-on-insulator (SOI) pixel sensors, “XRPIX,” are being developed for the next-generation x-ray astronomical satellite, “FORCE.” The XRPIX is fabricated with the SOI technology, which makes it possible to integrate a high-resistivity Si sensor and a low-resistivity Si complementary metal oxide semiconductor (CMOS) circuit. The CMOS circuit in each pixel is equipped with a trigger function, allowing us to read out outputs only from the pixels with x-ray signals at the timing of x-ray detection. This function thus realizes high throughput and high time resolution, which enables to employ anti-coincidence technique for background rejection. A new series of XRPIX named XRPIX6E developed with a pinned depleted diode (PDD) structure improves spectral performance by suppressing the interference between the sensor and circuit layers. When semiconductor x-ray sensors are used in space, their spectral performance is generally degraded owing to the radiation damage caused by high-energy protons. Therefore, before using an XRPIX in space, it is necessary to evaluate the extent of degradation of its spectral performance by radiation damage. Thus, we performed a proton irradiation experiment for XRPIX6E for the first time at Heavy Ion Medical Accelerator in Chiba in the National Institute of Radiological Sciences. We irradiated XRPIX6E with high-energy protons with a total dose of up to 40 krad, equivalent to 400 years of irradiation in orbit. The 40-krad irradiation degraded the energy resolution of XRPIX6E by 25 ± 3 % , yielding an energy resolution of 260.1 ± 5.6 eV at the full-width half maximum for 5.9 keV X-rays. However, the value satisfies the requirement for FORCE, 300 eV at 6 keV, even after the irradiation. It was also found that the PDD XRPIX has enhanced radiation hardness compared to previous XRPIX devices. In addition, we investigated the degradation of the energy resolution; it was shown that the degradation would be due to increasing energy-independent components, e.g., readout noise.

Anomaly detection with variational quantum generative adversarial networks

Generative adversarial networks (GANs) are a machine learning framework comprising a generative model for sampling from a target distribution and a discriminative model for evaluating the proximity of a sample to the target distribution. GANs exhibit strong performance in imaging or anomaly detection. However, they suffer from training instabilities, and sampling efficiency may be limited by the classical sampling procedure. We introduce variational quantum–classical Wasserstein GANs (WGANs) to address these issues and embed this model in a classical machine learning framework for anomaly detection. Classical WGANs improve training stability by using a cost function better suited for gradient descent. Our model replaces the generator of WGANs with a hybrid quantum–classical neural net and leaves the classical discriminative model unchanged. This way, high-dimensional classical data only enters the classical model and need not be prepared in a quantum circuit. We demonstrate the effectiveness of this method on a credit card fraud dataset. For this dataset our method shows performance on par with classical methods in terms of the F 1 score. We analyze the influence of the circuit ansatz, layer width and depth, neural net architecture parameter initialization strategy, and sampling noise on convergence and performance.

Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs

The use of through silicon vias (TSVs) is essential for vertically connecting the individual circuit layers of a 3-D IC. However, because the pitch between TSVs is being decreased, it becomes more vulnerable to bridge defects between the TSVs. In the previous architectures, the parallel topology between the power supply and the bridge defects reduces the resolution of the test results and makes them very sensitive to process variations. In this article, an enhanced postbond test architecture that improves the testability of bridge defects screening with a floating control circuit of supply voltage driver is proposed. The proposed structure allows the selective formation of a series circuit that includes the supply voltage driver and bridge defects between the TSVs; the structure can improve the output voltage resolution of the bridge defects by 27.2 times over that of the previous architectures. According to the experimental results, while exhibiting a proper test time, hardware overhead, and peak current consumption for mass production, the system guarantees testability for the detection of bridge defects. Moreover, the Monte Carlo simulation results show that the proposed architecture has a higher test reliability under process variations than the current test architectures.

Low-Temperature Deep Ultraviolet Laser Polycrystallization of Amorphous Silicon for Monolithic 3-Dimension Integration

Monolithic 3-dimensional integration (M3D) requires heat treatment techniques that should not degrade the device performance of the lower layers when applied to device fabrication in the upper layers. Deep ultraviolet (DUV) laser annealing was implemented in the crystallization of amorphous silicon and source/drain junction activation to fabricate polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect-transistors (MOSFETs) for upper-layer devices. The poly-Si MOSFET devices were fabricated successfully on top of the bottom electronic circuit layer (isolated by a thick silicon dioxide layer). Devices on the upper and lower layers were connected through interlayer vias to form a current-starved ring oscillator. The current-to-frequency converter on the bottom layer showed a reasonable increase in frequency as the current of the poly-Si MOSFET on the upper layer increased with increasing silicon grain size, confirming that DUV laser annealing did not degrade the performance of the bottom layer devices. This opens more opportunities for using DUV laser annealing in the M3D integration.

Active Thermal Management of High-Power LED Through Chip on Thermoelectric Cooler

In this work, we proposed a chip on thermoelectric cooler (chip-on-TEC) for the active thermal management of high-power light-emitting diode (LED). The chip-on-TEC was prepared by electroplating a circuit layer on the cold-side substrate of thermoelectric cooling (TEC) and directly attaching LED chips on the circuit layer. Due to the Peltier effect of TE materials and the low thermal resistance of chip-on-TEC structure, the heat generated from the chips can be dissipated to the surrounding environment effectively. The performances of chip-on-TEC were studied by using the thermal simulation and packaging experiment. Compared with the traditional packaging structure, the working temperature of chip-on-TEC is greatly reduced under various chip currents. At the chip current of 1.0 A, the chip-on-TEC can reduce the working temperature from 232 °C to 114 °C (the reduction of 51%). Moreover, the light output power of LED is increased by 35.3%. The chip-on-TEC also can improve the light intensity and the light saturation point of LED. The results demonstrate that the chip-on-TEC is a promising thermal management for high-power LED packaging.

Quantum Generative Models for Small Molecule Drug Discovery

Existing drug discovery pipelines take 5-10 years and cost billions of dollars. Computational approaches aim to sample from regions of the whole molecular and solid-state compounds called chemical space which could be on the order of 1060 . Deep generative models can model the underlying probability distribution of both the physical structures and property of drugs and relate them nonlinearly. By exploiting patterns in massive datasets, these models can distill salient features that characterize the molecules. Generative Adversarial Networks (GANs) discover drug candidates by generating molecular structures that obey chemical and physical properties and show affinity towards binding with the receptor for a target disease. However, classical GANs cannot explore certain regions of the chemical space and suffer from curse-of-dimensionality. A full quantum GAN may require more than 90 qubits even to generate QM9-like small molecules. We propose a qubit-efficient quantum GAN with a hybrid generator (QGAN-HG) to learn richer representation of molecules via searching exponentially large chemical space with few qubits more efficiently than classical GAN. The QGANHG model is composed of a hybrid quantum generator that supports various number of qubits and quantum circuit layers, and, a classical discriminator. QGAN-HG with only 14.93% retained parameters can learn molecular distribution as efficiently as classical counterpart. The QGAN-HG variation with patched circuits considerably accelerates our standard QGANHG training process and avoids potential gradient vanishing issue of deep neural networks. Code is available on GitHub https://github.com/jundeli/quantum-gan.

Spectroscopic performance improvement of SOI pixel detector for X-ray astronomy by introducing Double-SOI structure

This paper reports the spectroscopic performance improvement of the silicon-on-insulator (SOI) pixel detector for X-ray astronomy, by introducing a double-SOI (D-SOI) structure. For applications in X-ray astronomical observatories, we have been developing a series of monolithic active pixel sensors, named as “XRPIXs,” based on SOI pixel technology. The D-SOI structure has an advantage that it can suppress a parasitic capacitance between the sensing node and the circuit layer, due to which the closed-loop gain cannot be increased in our conventional XRPIXs with a single-SOI (S-SOI) structure. Compared to the S-SOI XRPIX, the closed-loop gain is doubled in the D-SOI XRPIX. The readout noise is effectively lowered to 33% (16 e− (rms)), and the energy resolution at 6.4 keV is improved by a factor of 1.7 (290 eV in FWHM). The suppression of the parasitic capacitance is also quantitatively evaluated based on the results of capacitance extraction simulation from the layout. This evaluation provides design guidelines for further reduction of the readout noise.

Simultaneous Measurement for Thickness and P Content of an Electroless Ni/Au Plating Film on Printed Circuit Board by XRF Spectrometry

X-ray fluorescence spectrometry (XRF) is one of the methods to measure the plating thickness. It is widely used for the quality control of plating, because it can measure the film thickness of multilayer plating and the composition of alloy layers with nondestructive and contactless method. Thus, XRF thickness analyzers are available today. Printed circuit boards (PCBs) are one of the targets of an XRF thickness analyzer. The common structure of PCBs is Cu/Ni/Au, the Ni and Au double layer plating on a Cu circuit layer. Recently, electroless nickel plating is used widely instead of electric nickel plating because of various requests from electric product manufacturers. The electroless nickel is an alloy of nickel and phosphorus, and the phosphorus concentration is important for plating quality control. However it was difficult for XRF thickness analyzers to measure the nickel layer thickness and the phosphorus concentration without removing gold plating. We have newly developed a correction method for simultaneous measurement of the respective Ni and Au layers thickness and the phosphorus concentration using XRF. We report on the latest cases of measuring the plating layer thickness and the phosphorus concentration of PCBs with our new developed method.

Ultrahigh-performance integrated inverters based on amorphous zinc tin oxide deposited at room temperature

Recent advances in the field of integrated circuits based on sustainable and transparent amorphous oxide semiconductors (AOSs) are presented, demonstrating ultrahigh performance operating state-of-the-art integrated inverters comprising metal–semiconductor field-effect transistors (MESFETs) with amorphous zinc tin oxide (ZTO) as a channel material. All individual circuit layers have been deposited entirely at room temperature, and the completed devices did not require undergoing additional thermal annealing treatment in order to facilitate proper device functionality. The demonstrated ZTO-based MESFETs exhibit current on/off ratios of over 8 orders of magnitude a field-effect mobility of 8.4 cm2 V−1 s−1, and they can be switched within a voltage range of less than 1.5 V attributed to their small subthreshold swing as low as 86 mV decade−1. Due to adjustments of the circuit layout and, thus, the improvement of certain geometry-related transistor properties, the associated Schottky diode FET logic inverters facilitate low-voltage switching by exhibiting a remarkable maximum voltage gain of up to 1190 with transition voltages of only 80 mV while operating at low supply voltages ≤3 V and maintaining a stable device performance under level shift. To the best of our knowledge, the presented integrated inverters clearly exceed the performance of any similar previously reported devices based on AOS, and thus, prove the enormous potential of amorphous ZTO for sustainable, scalable low-power electronics within future flexible and transparent applications.