Lattice Wave Digital Filters Research Articles

Optimal design of lattice wave digital fractional‐order Butterworth filter

SummaryThis letter presents the design of digital fractional‐order Butterworth filter (DFOBF) of order (n+α), where n is an integer, and α ∈ (0,1), from the perspective of optimal realization. The magnitude–frequency characteristic of the DFOBF is optimally modeled using the computationally efficient lattice wave digital filters (LWDFs). Design examples for the third‐ and fifth‐order LWDF‐DFOBFs with various values of n, α, and cut‐off frequencies are presented.

Hardware Emulation of a Biorthogonal Wavelet Transform-Based Heart Rate Monitoring Device

In this work, a low-power, area-efficient, and high-performance electrocardiogram (ECG) detector that can be used in modern implantable cardiac pacemaker systems is proposed. Qualitative and quantitative analysis indicates that the Biorthogonal-3.1 wavelet transform combined with adaptive slope prediction is best suited to detect various ECG peaks by effectively denoising various artifacts present in an ECG signal. A demand-based wavelet filter bank (WFB) architecture consisting of a series combination of three lowpass filters is the primary reason for the low-power requirements of the circuit. Power consumption and area requirements of the circuit are further reduced by realizing the lowpass filters using lattice wave digital filter realization that reduces the requirement of delay elements, and multipliers count by 80% and 75%, respectively. The proposed ECG denoising scheme using the biorthogonal 3.1 wavelet transform generates a smoother denoised ECG wave by retaining the important morphology of an ECG signal. Adaptive slope prediction criterion-based ECG processing and detection schemes achieve a high detection accuracy of 99.90%, with the lowest error of 0.002%. The proposed scheme is capable of distinguishing between a normal ECG, paced ECG, arrhythmic ECG, and low and high-resolution ECG. The proposed algorithm is then emulated on the Xilinx Ⓡ-Virtex Ⓡ-7 FPGA hardware platform. Power consumption, area, delay, and switching energy of the proposed ECG processing scheme are reduced when compared to existing ECG detection schemes and are found to be of $0.493~\mu \text{W}$ , 1.1 mm2, 10 ns, and $4.93~\mu \text{J}$ , respectively.

Design and FPGA implementation of lattice wave digital notch filter with minimal transient duration

In this study, the design and field-programmable gate array (FPGA) implementation of the digital notch filter with the lattice wave digital filter (LWDF) structure is presented. For reducing the initial signal transient, the variable notch bandwidth filter is designed. During the initial samples, the notch filter has a wide bandwidth in order to diminish signal transient. As time moves forward, the notch bandwidth reduces to attain the possible minimum width. This results in minimised transient duration notch filter with a sufficiently high-quality factor. Previously, the IIR structure has been used for implementing the time varying bandwidth notch filter. Such a filter requires two variable coefficients for varying the notch width with time. The advantage of using a LWDF structure is that only one coefficient has variable values to vary the notch width with time. Therefore, the number of memory locations required to implement the proposed design is reduced by half. Moreover, the LWDF is less sensitive to the word-length effects. Thus, the proposed lattice wave digital notch filter (LWDNF) produces better results compared to the existing literature in terms of error analysis. The suggested LWDNF is then implemented on a field-programmable gate array using a Xilinx system generator for the DSP design suite.

Design of efficient fractional operator for ECG signal detection in implantable cardiac pacemaker systems

SummaryA low power and high‐performance digital electrocardiogram (ECG) detector has become a basic requirement in modern implantable cardiac pacemakers. A fractional operator‐based digital ECG detector for modern pacemaker systems is proposed in this work. Instead of conventional thresholding, an adaptive slope prediction threshold is utilized for the detection of ECG peaks. A stochastic search‐based algorithm, namely, cuckoo search algorithm, is used to design an optimal fractional operator that is used for ECG denoising. It has been found that the proposed adaptive slope prediction threshold increases the QRS complex detection performance. A low detection error rate (DER) ranges from 0.01% to 0.56%, positive predictivity (P+) ranges from 99.32% to 99.98%, sensitivity (Se) ranges from 99.45% to 99.98%, and a detection accuracy (Acc) ranges from 99.43% to 99.96% for different databases are achieved for the proposed ECG detector, which is better compared with the existing ECG detectors. The proposed design of fractional order operator based on the lattice wave digital filter (LWDF) requires a minimum number of the multipliers for its structural realization.

Design and FPGA implementation of lattice wave fractional order digital differentiator

This paper deals with the design and FPGA implementation of a fractional order digital differentiator. It is realized using computationally efficient lattice wave digital filter (LWDF) which requires minimum multipliers in comparison to the direct form structure. A nature inspired ant lion optimization (ALO) algorithm is utilized to compute optimal coefficients of the LWDF based digital differentiator. The proposed LWDF based digital differentiator is compared with the existing literature in terms of magnitude response, percentage magnitude error and root mean square magnitude error. LWDF structure comprises of constant coefficient multipliers, adders and delay units which are implemented on FPGA with the help of Xilinx system generator for DSP design tool. For efficient implementation of multipliers, multiplier-less logic through digit recoding techniques such as canonic signed digit (CSD) representation and radix-2r encoding are described through Verilog HDL and incorporated in the implementation model as black box. Post-implementation results show that implementation based on the radix-2r encoding is found to be more efficient than that of the CSD encoding. The design and implementation results are also reported to highlight the improvements.

Design and FPGA implementation of 11th order Efficient IIR Wavelet Filter Banks with Approximate Linear-phase

In this paper. Bireciprocal Lattice Wave Digital Filters (BLWDFs) are utilized in an approximate linear-phase in pass-band design of order IIR wavelet filter banks (FBs). These filter banks are efficiently designed by replacement one of branches for (BLWDFs) by only a unit delay. The coefficients of the designed filter are achieved by simulating the IIR response suggested in [1]. The design is first simulated using Matlab programming in order to investigate the resulting wavelet filter properties and to find the suitable wordlength for the BLWDFs coefficients. FPGA implemtation of the proposed IIR wavelet filter bank is also achived for three levels with less complexity and high operating frequency.

Optimal design of minimum multiplier lattice wave digital lowpass filter using metaheuristic techniques

This study aims towards the efficient design of arbitrary-band and halfband lowpass (LP) filter based on lattice wave digital filter (LWDF) structure with the usage of minimal number of multipliers in its structural realisation. The designing of the LP filter is formulated as an optimisation problem where coefficients of LWDF transfer function are iteratively optimised by the evolutionary algorithms. The potential of four optimisation algorithms, real-coded genetic algorithm, particle swarm optimisation, differential evolution algorithm, and cuckoo search algorithm, are explored for determining the optimal LWDF coefficients by minimising the error objective function. The structural realisation of LP using LWDF structure enhances the design accuracy as the usage of multiplier prominently reduces. The simulation and statistical results of the proposed lattice wave digital lowpass filter (LWDLF) and bireciprocal lattice wave digital lowpass filter (BLWDLF) design show significant improvement in the mean square error, passband ripples, transition bandwidth, stopband attenuation, rate of convergence, and execution time. To manifest the efficient design of the proposed LWDLF and BLWDLF, the results are compared with the designed arbitrary-band, halfband canonic-LP filters and previous published works.

A Multipurpose PV System Integrated to a Three-Phase Distribution System Using an LWDF-Based Approach

This paper presents a multipurpose photovoltaic (PV) system using a lattice wave digital filter (LWDF)-based control approach. The multipurpose PV system is developed for integrating the active power to the distribution system with variable PV insolation and compensating the nonlinear loads connected at point-of-common coupling. The PV system is multifunctional; therefore, it serves various purposes. It injects the active power of solar PV array to the grid. It mitigates harmonics of loads and provides grid currents balancing. The PV system incorporates a PV array, a boost converter, a voltage-source converter (VSC), a nonlinear load, and a distribution system. The boost converter is utilized for maximum power extraction from PV array using an incremental-conductance-based maximum power point tracking technique. To control the grid-tied VSC, a LWDF-based control approach is proposed. In addition, this approach is able to produce the desired sinusoidal fundamental component of load current to estimate the grid reference currents. The aim is to implement this control as it has many properties like low-pass band sensitivity, good dynamic response, and reduction in a dc-offset noise error. The varieties of experimental results are presented to validate the control of a PV system.

Design and FPGA implementation of multiplierless comb filter

SummaryThe main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements; therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first‐order and second‐order all‐pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round‐off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan‐6 and Virtex‐6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright © 2017 John Wiley & Sons, Ltd.

Design of minimum multiplier fractional order differentiator based on lattice wave digital filter

In this paper, a novel design of fractional order differentiator (FOD) based on lattice wave digital filter (LWDF) is proposed which requires minimum number of multiplier for its structural realization. Firstly, the FOD design problem is formulated as an optimization problem using the transfer function of lattice wave digital filter. Then, three optimization algorithms, namely, genetic algorithm (GA), particle swarm optimization (PSO) and cuckoo search algorithm (CSA) are applied to determine the optimal LWDF coefficients. The realization of FOD using LWD structure increases the design accuracy, as only N number of coefficients are to be optimized for Nth order FOD. Finally, two design examples of 3rd and 5th order lattice wave digital fractional order differentiator (LWDFOD) are demonstrated to justify the design accuracy. The performance analysis of the proposed design is carried out based on magnitude response, absolute magnitude error (dB), root mean square (RMS) magnitude error, arithmetic complexity, convergence profile and computation time. Simulation results are attained to show the comparison of the proposed LWDFOD with the published works and it is observed that an improvement of 29% is obtained in the proposed design. The proposed LWDFOD approximates the ideal FOD and surpasses the existing ones reasonably well in mid and high frequency range, thereby making the proposed LWDFOD a promising technique for the design of digital FODs.

VLSI Implementation of Fixed-Point Lattice Wave Digital Filters for Increased Sampling Rate

VLSI Implementation of Fixed-Point Lattice Wave Digital Filters for Increased Sampling Rate

Grid integration of 3P4W solar PV system using M‐LWDF‐based control technique

This study proposes a multitasking three-phase four (3P4W) wire solar photovoltaic (SPV) system using a modified lattice wave digital filter (M-LWDF)-based control technique. For effective utilisation of SPV array, an incremental conductance-based maximum power point tracking approach is used to obtain the peak power. However, M-LWDF-based control technique is used to control the grid tied 4-leg voltage source converter. The proposed control technique with reduced computational burden is an analytical tool for extracting the harmonics free fundamental component of load current and the mitigation of load neutral current. The M-LWDF-based control technique is implemented under various working modes at non-linear loads.

Genetic-Based IIR Filter Design for Efficient QRS Complex Detection using Neuro-Based Classifier

In this paper, a new method is proposed for QRS complex detectionusing a special kind of IIR filter called bi-reciprocal lattice wave digital filter (WDF). This filter has some attractive features that make it more efficient than other types of filters.One of these features is its sufficient linear phase in the passband, thus yielding a perfect reconstraction condition. Therefore, it is not required to cascade the designed filter with anall-pass filter for correcting the phase distortion. The coefficients of the designedfilter areachieved by simulating the FIR response suggested in [1].A least square method solution is usedin such simulation with a genetic-based algorithm.A simplified structure for the designed filter is accomplished with less-complex realization. 50records of European ST – T ECG database is classified into four classes (Normal, Left Bundle Branch Block (LBBB), ST segment elevation, and Left Ventricular Hypertrophy (LVH)). By applying the designed filter coefficients into neural network classifier, the results show that the accuracy of the classification process is 95.9 %.

VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency

VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency Low complexity and high speed are the key requirements of the digital filters. These filters can be realized using all-pass sections. In this paper, design and minimum hardware implementation of a fixed point lattice wave digital filter based on three port series adaptor is proposed. Here, the second-order all-pass sections are replaced with three port series adaptors. A design-level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques. The proposed implementation reduces the latency of the critical loop by reducing the number of components (adders and multipliers).

Design and Implementation of DWMT Transmission Systems using IIR Wavelet Filter Banks

Multicarrier modulation using orthogonal frequency division multiplexing (OFDM) is often recognized as an efficient solution for wireless communications. However, waveform bases other than sinusoidal functions can similarly be used for multicarrier systems in order to provide an alternative to OFDM. In this context, DWMT transmission systems are suggested. It is known that such systems suffer obviously from the two main problems of Inter Symbol Interference (ISI) and Inter-Carrier Interference (ICI). ISI may be considerably reduced via channel equalization. The effect of ICI can be reduced using high order Finite Impulse Response(FIR)wavelet filter banks, but at the expense of increased system complexity. Those FIR banks which are required to reduce effect the ICI should have autocorrelation functions approaching an impulse. On other hand, Infinite Impulse Response(IIR) filter banks can be used to replace those FIR counterparts to increase sub-band discrimination while reducing the required filter order, i.e., decreasing the complexity of system. In this paper, a special type of IIR filter banks is designed and implemented for such purpose. Bi- reciprocal lattice wave digital filters (BLWDFs) are utilized in an approximate linear phase design of 11th order IIR wavelet filter bank (FB) for discrete wavelet multi-tone (DWMT) transmission systems. The performances of the proposed DWMT for transmission over simulated wireless channels with additive white Gaussian noise (AWGN) are examined and compared with one of the recent FIR designs. Significant improvements over the classical DWMT approach are observed.

FPGA Implementations of Bireciprocal Lattice Wave Discrete Wavelet Filter Banks

In this paper, a special type of IIR filter banks; that is the bireciprocal lattice wave digital filter (BLWDF) bank, is presented to simulate scaling and wavelet functions of six-level wavelet transform. 1st order all-pass sections are utilized for the realization of such filter banks in wave lattice structures. The resulting structures are a bireciprocal lattice wave discrete wavelet filter banks (BLW-DWFBs). Implementation of these BLW-DWFBs are accomplished on Spartan-3E FPGA kit. Implementation complexity and operating frequency characteristics of such discrete wavelet 5th order filter bank is proved to be comparable to the corresponding characteristics of the lifting scheme implementation of Bio. 5/3 wavelet filter bank. On the other hand, such IIR filter banks possess superior band discriminations and perfect roll-off frequency characteristics when compared to their Bio. 5/3 wavelet FIR counterparts.

An Analytical Design Procedure For Bireciprocal Lattice Wave Digital Filters With Approximate Linear Phase

A simple analytic design procedure for bireciprocal lattice wave digital filters (bireciprocal LWDFs) is presented with approximate linear phase. The design is started by replacing the odd order all-pass filter branch in the bireciprocal LWDF with a pure delay, leaving the other branch as an all-pass even function of z -2. Analytic design procedure is then formulated. Several design examples using such procedure are given for verifications. Keywords: Bireciprocal LWDFs, All-pass sections, Half-band filters, Approximate linear phase.

A 100 MS/s 4 MHz Bandwidth 70 dB SNR $\Delta \Sigma$ ADC in 90 nm CMOS

This paper describes the results of an implementation of a high speed DeltaSigma ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The DeltaSigma ADC is based on a switched-capacitor fourth-order single-loop DeltaSigma modulator with a 4-bit quantizer. The ADC uses a triple sampling technique and a two-step summation scheme for low power and high speed operation. Also, a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is implemented in the same process. The decimation filter is based on a polyphase IIR filter with a decimation ratio of 5, while the channel selection filter is based on two path lattice wave digital IIR filter. The ADC achieves 69.95 dB SNR and 66.85 dB SNDR over a 4 MHz bandwidth with a sampling frequency of 100 MHz. The fabricated DeltaSigma ADC and the digital signal processing block occupy 0.53 mm2 and 0.09 mm2, and consume 11.76 mW per channel.

A Systematic Algorithm for the Design of Lattice Wave Digital Filters With Short-Coefficient Wordlength

This paper describes an efficient algorithm for designing lattice wave digital (LWD) filters (parallel connections of two all-pass filters) with short-coefficient wordlength. The coefficient optimization is performed using the following three steps. First, an initial infinite-precision filter is designed such that it exceeds the given criteria in order to provide some tolerance for coefficient quantization. Second, a nonlinear optimization algorithm is used for determining a parameter space of the infinite-precision coefficients including the feasible space where the filter meets the given criteria. The third step involves finding the filter parameters in this space so that the resulting filter meets the given criteria with the simplest coefficient representation forms. The proposed algorithm guarantees that the optimum finite-precision solution can be found for both the fixed-point binary and multiplierless coefficient representation forms. In addition, this algorithm is applicable for producing the desired finite-precision solutions for both conventional and approximately linear-phase LWD filters. Comparisons with some other existing quantization schemes show that the proposed algorithm gives the best finite-precision solutions in all examples taken from the literature.

Design of Wave Digital Lattice Filters with Flat Passband, Equiripple Stopband and Nearly Constant Group Delay

Abstract A design method for wave digital lattice filters is presented which yields filters with maximally flat magnitude behaviour in the passband, equiripple in the stopband, and nearly constant group delay over the entire frequency range. The method starts with the specification of ideal allpass phases which produce the desired behaviour and then these specifications are approximated withactual allpasses. Equations for obtaining the allpasses and an algorithm for distributing the transmission zeros to give equiripple magnitude behaviour in the stopband are included as well as examples obtained with the design method.