Lateral Diffused MOSFET Research Articles

Simulation of a new hybrid Si/SiC power device for harsh environment applications

A new power device structure is proposed, conceived to operate in a high temperature, harsh environment, for example within a motor drive application down hole, as an inverter in the engine bay of an electric car, or as a solar inverter in space. The lateral silicon power device resembles a laterally diffused MOSFET (LDMOS), such as those implemented within silicon on insulator (SOI) substrates. However, unlike SOI, the Si thin film has been transferred directly onto a semi-insulating 6H silicon carbide (6H-SiC) substrate via a wafer bonding process. Thermal simulations of the hybrid Si/SiC substrate have shown that the high thermal conductivity of the SiC will have a junction-to-case temperature approximately 4 times less that an equivalent SOI device, reducing the effects of self-heating. Electrical simulations of a 600 V power device, implemented entirely with the silicon thin film, suggest that it will retain the ability of SOI to minimise leakage at high temperature, but does so with 50% less conduction losses.

Gate-Controlled Reverse Recovery for Characterization of LDMOS Body Diode

Reverse recovery behavior is a useful tool for monitoring lifetime variations in the body diode of power MOSFETs. However, correct interpretation of the laterally diffused MOSFET (LDMOS) reverse recovery is challenging and requires special attention. This is due to the fact that the stored charges in the LDMOS drift region can flow from two different directions with each having different lifetime values. By studying the effects of diode reverse bias and gate voltage on the current flow direction during the reverse recovery, we present a simple approach to extract meaningful lifetime values, which can be used to determine material quality at different locations in the drift region of the LDMOS devices.

Design of a Reliable p-Channel LDMOS FET With RESURF Technology

High-voltage lateral diffused MOS (LDMOS) FETs have been widely developed and studied for analog application. High-temperature reverse bias (HTRB) instability is one of the largest concerns for this device in achieving high reliability guaranteeing performance stability. This paper focuses on a lower RON approach for 200 V p-channel LDMOS FET with a reduced surface electric field technique, where effectiveness of the drift profile optimization is proposed. Then, HTRB degradation phenomenon relating RON and BVOFF shift was focused on. Through the analysis via device simulation, HTRB shift phenomenon was found to be well simulated with the electron trap feature in the field oxide over the drift region, where the electron was generated by impact ionization under a high-voltage reverse bias stress condition. The technique using a metal field plate for improving impact ionization voltage with maintenance of RON is also proposed for stable p-channel LDMOS FETs that can deliver reliable and high-performance applications.

Experimental Investigation and Analysis of the LDMOS FET Breakdown Under HPM Pulses

In this paper, thermal breakdown effects in a laterally diffused MOS (LDMOS) FET under the impact of high-power microwave (HPM) pulses are investigated by theoretically analyzing, modeling, and measuring. Experimental investigations of the LDMOS FET-based power amplifier (PA) are performed under different pulse durations. The measurement system consists of an adjustable HPM source, one controller, couplers, limiters, attenuators, one four-channel oscilloscope, and a DUT. By increasing the input pulse power level, electrothermal breakdown is observed. The breakdown temperature is calculated by using a 2-D analytic model based on the measured power to failure data. Then, our developed time-domain finite-element numerical algorithm is used to characterize temperature distribution and transient performance of the LDMOS FET. The energy capability, which defines the maximum energy that the device can handle, is 15.5 mJ under the pulse duration of 1 ms with a breakdown temperature of 605 K.

Design for Reliability: The RF Power LDMOSFET

The design of lateral diffused MOSFETs operating under continuous peak power in RF communication applications is one of the most demanding among semiconductor applications. This paper discusses design parameters related to the optimum performance of the transistor and constraints introduced by the fabrication process in achieving them. Nonstandard processing steps include thick pad oxides, a sinker to connect source to the bottom substrate, metal silicided gates, a source shield over the drift region, and often gold metallization for improved electromigration. Additionally, the device requires careful optimization for control of hot-carrier-related bias drift. The impact of negative charge injection in the gate oxide is to degrade the power gain and at higher output power levels, the linearity. The difficulties in assessment of the true impact of hot carriers on these parameters via measurement are highlighted. The contribution of matching impedances and class of bias on hot-carrier degradation is extracted via modeling. A ldquodesign for reliabilityrdquo approach for this product is investigated with four designs of the drift region, evaluated in terms of transconductance, on-resistance, breakdown voltage, capacitance, and hot-carrier immunity. A second-generation source shield demonstrates a tradeoff via significant reduction of feedback capacitance at a cost to transconductance. A deep drift design shows optimization in terms of gain without compromise to the hot-carrier immunity. Recent advances made in terms of packaging and electromigration are reviewed.

Thick-Strained-Si/Relaxed-SiGe Structure of High-Performance RF Power LDMOSFETs for Cellular Handsets

A strained-Si/relaxed-SiGe structure was applied to laterally diffused MOSFETs (LDMOSFETs) in order to improve the PAE of cellular handset RF power-amplifier applications. The LDMOSFETs were fabricated in a 70-nm-thick strained-Si/relaxed-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.85</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.15</sub> structure. Despite the appearance of misfit dislocations, the thick strained-Si was essential for high efficiency and low leakage. The self-heating effects on the power performance were estimated to be negligible by using dynamic thermal simulation. The devices exhibited 46.6% PAE at a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> of 27.5 dBm for wideband code-division multiple-access handset applications, which was a 3.8-point improvement over Si controls

Impact of substrate-surface potential on the performance of RF power LDMOSFETs on high-resistivity SOI

This paper presents an in-depth study of the effects of substrate-surface potential on the RF power performance of laterally diffused MOSFETs (LDMOSFETs) fabricated on high-resistivity silicon-on-insulator (HR-SOI). Substrate-surface inversion and accumulation substantially degrade the RF power performance of these devices by providing an RF shunt between source and drain through the substrate surface. The degradation is most prominent under conditions of low gain, high frequency, and high power compression. The potential of HR-SOI for RF applications can only be realized by preventing the appearance of a continuous conducting path at the substrate surface. Under appropriate conditions of substrate-surface depletion, an RF power LDMOSFET on HR-SOI with a peak PAE of 40% at 7.2 GHz is demonstrated

Effect of Mobile Charge on Hot-Carrier Degradation in Lateral Diffused MOSFET

Hot carrier-induced device degradation in n-type lateral diffused MOSFETs with mobile charges in gate oxide has been studied. Abnormal decrease-then-increase in V/sub th/ during hot-carrier stress was observed. The decrease was found to be caused by movement of mobile charges while the increase was the normally observed hot-electron degradation. The hot-electron degradation was drastically accelerated with the presence of mobile charges and easily recovered after baking or negative gate bias. The magnitude of degradation linearly increases with mobile charge density. The acceptable limits of mobile charge density have been estimated. The observed behaviors are very similar to positive charging processes found in other n-MOSFETs that were attributed to hot-hole effects, suggesting mobile charge induced degradation must be carefully excluded in hot-hole injection studies.