Laterally Diffused Metal Oxide Semiconductor Transistor Research Articles

Research on single event effects and hardening design of LDMOS transistors

In this paper, an N-type Lateral Diffused Metal Oxide Semiconductor (LDMOS) device was designed using a heavily doped P+ well and drain N-type buffer layer structure in the BCD process. The hardened mechanism of heavily doped P+ well and drain N-type buffer layer structures was simulated and analyzed using a TCAD device simulator. To verify the anti-SEE performance of the LDMOS, the irradiation test was conducted using Ta ion (LET = 79.2 MeV·cm−2 mg−1). The results show that increasing P+ well doping concentration and using buffer layer structure can increase the single event burnout (SEB) voltage of high-voltage LDMOS devices. SEB did not occur within the full operation voltage range.

Comprehensive study of the radiation effects on the LDMOS transistors

The reliability of power devices is attracting more and more attention, especially in the extreme radiation environment. The laterally diffused metal–oxide–semiconductor (LDMOS) has been widely used in high voltage integrated circuits. In this paper, the radiation effects of LDMOS transistors are extensively investigated through three-dimensional (3D) TCAD simulations, including Total-Ionizing Dose (TID), Single-Event Effect (SEE) and Transient Dose Rate Effect (TDRE). Firstly, the mechanism of TID effect on the LDMOS is revealed in consideration of temperature variations. Secondly, the single-event effect of the LDMOS is studied with different incident positions, linear energy transfer (LET) values, incident lengths, incident angles, bias conditions and temperatures. Besides, the combined effect of total-ionizing dose and single-event burnout is characterized. Finally, transient response of the LDMOS under transient γ radiation is also studied comprehensively. Therefore, it gives an insight into the physical mechanisms and response characteristics of complex radiation effects, which can provide guidance for radiation-hardened by design and application of the LDMOS devices.

A simulation-based evaluation of single-event burnout mechanisms and varied SEB hardening designs in power LDMOS transistors

In this paper, the Single-event burnout (SEB) triggering mechanism for laterally-diffused metal-oxide semiconductor (LDMOS) devices is numerically studied by using the 2D technology computer-aided design device simulator, simultaneously, three hardening designs are proposed for the first time. SEB triggering voltage (VSEB) are extracted and compared between the four structures when the heavy ion with a same linear energy transfer (LET) of 0.2pC/μm strikes the most sensitive point of the devices. The occurrence mechanism of SEB in LDMOS is mainly due to avalanche breakdown caused by high electric field, which further triggers the parasitic BJT and eventually forms regenerative feedback. By comparing the simulation results between conventional LDMOS and proposed hardened LDMOS designs, the VSEB are 197 V of conventional LDMOS, 306 V of NB LDMOS, 291 V of NP LDMOS and 394 V of NP-BP LDMOS, and their breakdown voltage(BV) are 650 V,606 V, 555 V and 553 V respectively. With different LET values, NB LDMOS and NP LDMOS also have better SEB performance than the conventional one.

IFMIF-DONES RF System

The IFMIF-DONES accelerator cavities require around 5.7 MW of continuous RF power at 175 MHz to deliver a 125 mA and 40 MeV deuteron beam at the lithium target. The IFMIF-DONES RF System is composed of 56 RF Stations able to provide up to 200 kW RF power at 175 MHz in CW, delivering a grand total of 7.4 MW.Such a massive system requires an ambitious approach to be able to comply with the accelerator requirements with a high efficiency and a high availability. The newest advancements in the field of RF systems for accelerators, which are already implemented independently in some facilities, are integrated for the first time in a single system from the early design phases. The result of this approach is the RF Station, which is a totally independent and compact RF module containing all the components needed to feed, control, and protect the accelerator cavities. The amplification technology chosen is the Laterally-Diffused Metal-Oxide Semiconductor (LDMOS) transistor, providing a good efficiency and high robustness. The proposed RF power combination of up to 160 transistors is based on resonant cavity combiner, allowing a single-step combination that highly reduces the losses with respect to more traditional corporate combining schemes. In this proposal, the RF generation relies on a fully digital Low-Level RF (LLRF) providing accurate amplitude/phase control and high flexibility to implement all the required functions for a proper cavity operation. The RF Station has been designed maximizing the modularity and the reliability. In order to achieve the required modularity, the LDMOS transistors have been grouped in Amplifier Modules (AMDs) containing four of them but keeping independent outputs. Furthermore, the AC/DC power converters have also been grouped in modules feeding a common DC bus. The RF Station will have redundant modules to be able to operate properly in any condition, even with some of them failed.This innovative proposal for the IFMIF-DONES RF System design and detailed information on the RF Stations architecture are presented in this paper.

Simulation Study on the Optimization and Scaling Behavior of LDMOS Transistors for Low-Voltage Power Applications

We present a systematic investigation of device optimization for laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors in terms of subthreshold leakage current, breakdown voltage, and ON-resistance for low-voltage ( $10\boldsymbol {^{-13}}\text{A}/\boldsymbol {\mu }\text{m}$ while maintaining a breakdown voltage exceeding 10 V for channel lengths down to 10 nm. Interestingly, we find an optimal ON-resistance for a channel length of 40 nm, while for shorter channel lengths the ON-state resistance increases with decreasing channel length. The increasing resistance for shorter channels is caused by electron mobility degradation as a result of an increasing body doping, needed to limit the leakage current. The optimal channel length presents a limit to conventional scaling of LDMOS devices, commonly used in low-voltage power applications.

A new low specific on-resistance Hk-LDMOS with N-poly diode

A new structure of the laterally diffused metal–oxide–semiconductor transistors (LDMOS) using a high permittivity (Hk) dielectric is proposed, and its mechanism is investigated by 2-D TCAD simulation. The breakdown voltage (BV) is remarkably increased by using the Hk dielectric. Moreover, a reverse biased poly diode is first introduced on the Hk dielectric, which assists the n-drift region forming an electron accumulation layer to reduce the specific on-resistance (Ron,sp) further. Compared with a conventional LDMOS with the same geometry, the BV increases by 24%, and the Ron,sp decreases approximately by 50%. Besides, the proposed structure is less sensitive to the n-drift region doping deviation, and exhibits a larger safe operating area (SOA).

Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy**Project supported by the Chinese National Key Project (No. 2012ZX02502).

A laterally diffused metal–oxide–semiconductor (LDMOS) device design with an enhanced p-well and double p-epitaxial structure is investigated for device ruggedness improvement while keeping its high device performance under high frequency. Based upon the device design, radio-frequency (RF) LDMOS transistors for GSM (global system for mobile communication) application have been fabricated by using 0.35 μm CMOS technologies. Experimental data show that the proposed device achieves a breakdown voltage of 70 V, output power of 180 W. The RF linear gain is over 20 dB and the power added efficiency (PAE) is over 70% with the frequency of 920 MHz. In particular, it can pass the 20 : 1 voltage standing wave ratio (VSWR) load mismatch biased at drain DC supply voltage of 32 V and output power at 10-dB gain compression point (P10dB). The device ruggedness has been remarkably improved by using the proposed device structure.

Elimination of stress induced dislocation in deep Poly Sinker LDMOS technology

This work investigates the leakage current of power LDMOS (laterally diffused metal–oxide–semiconductor) transistors with deep poly sinker, and the leakage shows a certain wafer map distribution with most of the failed dies located at the center area. It is found that the leakage current is mainly caused by the stress-induced dislocations close to the deep poly sinker. The relationship between the stress-induced dislocation (SID) and the wafer warpage is studied. Experimental results show the dislocation and the resulting leakage current can be effectively eliminated, by either modifying the device layout or optimizing the fabrication process of the poly sinker.

Power performance of 65 nm CMOS integrated LDMOS transistors at WLAN and X-band frequencies

Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10 V breakdown voltage have been implemented in a 65 nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8 GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5 V supply voltage. Results at 2.45 GHz showed 290 mW/mm output power density with 17 dB linear gain and over 45% power added efficiency (PAE) at 4 dB compression at a supply voltage of 5 V. Furthermore, results in X-band at 8 GHz show 8 dB linear gain, 320 mW/mm output power density and over 22% PAE at 4 dB compression. Third-order intermodulation measurements at 8 GHz revealed OIP3 of 18.9 and 21.9 dBm at 3.3 and 5 V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26 h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65 nm CMOS process without extra process steps.

Two‐stage hot‐carrier‐induced degradation of p‐type LDMOS transistors

Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal–oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current–voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.

Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection

The trigger voltage walk-in effect has been investigated by designing two different laterally diffused metal—oxide—semiconductor (LDMOS) transistors with an embedded silicon controlled rectifier (SCR). By inserting a P+ implant region along the outer and the inner boundary of the N+ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5 μm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse (TLP) and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.

High temperature behavior of multi-region direct current current–voltage spectroscopy and relationship with shallow-trench-isolation-based high-voltage laterally diffused metal–oxide–semiconductor field-effect-transistors reliability

With the process compatibility with the mainstream standard complementary metal–oxide–semiconductor (CMOS), shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular for its better tradeoff between breakdown voltage and performance, especially for smart power applications. A multi-region direct current current–voltage (MR-DCIV) technique with spectroscopic features was demonstrated to map the interface state generation in the channel, accumulation and STI drift regions. High temperature behavior of MR-DCIV spectroscopy was analyzed and a physical model was verified. Degradation of STI-based LDMOS transistors under high temperature reverse bias (HTRB) stress is experimentally studied by MR-DCIV spectroscopy. The impact of interface state location on device electrical characteristics was investigated. Our results show that the major contribution to HTRB degradation, in term of the on-resistance degradation, was attributed to interface state generation under STI drift region.

An Ultralow Specific ON-Resistance LDMOST Using Charge Balance by Split p-Gate and n-Drift Regions

A laterally diffused metal-oxide-semiconductor transistor (LDMOST) with ultralow specific ON-resistance (Rsp) is studied. In the OFF-state, the split p-type gate is depleted to achieve charge compensation with the n-type drift region, allowing a high n-drift doping. In the ON-state, holes accumulate in the split p-gate because the gate voltage (VG) applied induces simultaneously electron accumulation in the n-type drift region, enabling the on-current density to be not limited by the drift doping concentration and resulting in an ultralow value of Rsp. Moreover, the accumulated hole charges are stored in a capacitor during the turn-off process and are restored during the turn-on process, without an increase of the effective gate charge (Qg). Simulation results show good agreement with the theory. A 600 V device has an Rsp of <;50% of the conventional double-RESURF LDMOST with the effective Qg being almost the same.

Nonlinear modeling of LDMOS transistors for high‐power FM transmitters

SUMMARYIn this paper, a nonlinear model of a commercial 10‐W laterally diffused metal oxide semiconductor (LDMOS) transistor for FM transmitters is identified. It is based on high‐frequency small‐signal measurements for the identification of both the parasitic network and the strictly nonlinear dynamic effects, whereas low‐frequency large‐signal measurements are exploited for the description of the dynamic I/V characteristics of the device above the cut‐off of low‐frequency dispersion. A validation of the proposed model is provided by using time‐domain nonlinear measurements carried out at 40 MHz and 100 MHz. Copyright © 2013 John Wiley &amp; Sons, Ltd.

Performance Improvement in RF LDMOS Transistors Using Wider Drain Contact

In this letter, we proposed a new layout structure for RF laterally diffused metal-oxide-semiconductor (LDMOS) transistors. In a multifinger layout, the drain contact region was designed to be wider than the channel region. The wider drain increases the equivalent drift region width to reduce the drift resistance and suppress the quasi-saturation effect. We found that the wide-drain multifinger LDMOS devices have lower on-resistance, higher cutoff frequency, higher maximum oscillation frequency, and better power performances than the standard multifinger ones.

Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide

Characteristics of lateral diffused metal–oxide–semiconductor (LDMOS) transistors with gradual junction profile by self-alignment implant through dual thicknesses of screen oxide are presented in this letter. Compared with LDMOS transistors with traditional junction profile, this new device shows improved off-state breakdown voltage, less severe in Kirk effect, and wider electrical safe operating area; without sacrificing device drivability. Technology computer aided design (TCAD) simulation results reveal that this new device has smaller electric field both in off- and on-state bias conditions. Hot-carrier induced degradation of this new device under various stress conditions is also investigated and compared with that of the device with traditional junction profile.

Modelling of LDMOS transistor using artificial neural networks: DC and RF performances

This article presents an accurate method based on artificial neural networks (ANNs) for DC and RF modelling of laterally diffused metal oxide semiconductor (LDMOS) transistors, under various temperature conditions. In LDMOS transistors, temperature is an effective factor, so the proposed models include this parameter. Two neural networks‐based procedures have been proposed for LDMOS transistor modelling, first for DC and second for RF modelling. In each case, two kinds of neural networks have been used, multilayer perceptron and radial basis function neural networks. Two models are compared to each other in terms of accuracy, and for both of them, an excellent agreement between modelled and measured data is obtained. The ANN model is developed and trained with the help of data obtained by simulation of a Si‐LDMOS transistor using ADS software.

LDMOS Technology for RF Power Amplifiers

We show the status of laterally diffused metal-oxide-semiconductor (LDMOS) technology, which has been the device of choice for RF power applications for more than one decade. LDMOS fulfills the requirements for a wide range of class AB and pulsed applications, such as base station, broadcast, and microwave. We present state-of-the-art RF performance of the LDMOS transistor measured with a load-pull test setup, achieving class-AB drain efficiencies of 70% at 2 GHz for on-wafer and packaged devices. Furthermore, the results for several class-AB and Doherty amplifier implementations constructed with this technology are shown. As an illustration, a three-way Doherty application is demonstrated, which has a 7.5-dB back-off efficiency of 47% at 1.8 GHz with a peak power of 700 W and linearity numbers better than -65 dBc.

Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal–Oxide–Semiconductor Field-Effect Transistors by a Novel Direct Current Current–Voltage Technique

Shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal–oxide–semiconductor (CMOS) process. A novel direct current current–voltage (DCIV) technique demonstrated with multiple sharp peak signals is proposed to characterize interface state generation in the channel and in the STI drift regions separately. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by proposed technique. A two-dimensional numerical device simulation is performed to obtain insight into the proposed technique and device degradation characteristics under hot-carrier stress conditions. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our results show that the maximum Isub stress becomes the worst hot-carrier degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

Bandwidth enhancement of an inverse class-F power amplifier based on LDMOS devices

In this article, we report the design of an inverse class-F power amplifier for L-band transmit/receive module based on LDMOS (laterally diffused metal oxide semiconductor) transistors. The objective was to obtain high power efficiency over a wide band. Measurements showed a minimum of 61% power added efficiency (PAE) and 10 W output power with a gain of 14 dB over a bandwidth of 200 MHz. Average measured performances are, respectively, 11.4 W (±1.4 W) output power and 62.8% (±1.8%) PAE; 64.5% maximum PAE associated with 12.7 W output power has been reached. These results are, to our knowledge, the highest reported combination of power efficiency and bandwidth.