Lateral Metal Research Articles

Dielectrically Modulated Label Free Metal Controlled Organic Thin Film Transistor for Biosensing Applications

In this work, a novel structure of Dielectrically Modulated Organic Thin Film Transistor (OTFT) for biosensing applications is presented. The proposed device uses lateral metal contacts and an implanted metal with work function of 5.7 eV inside the organic material; as such it is being named as Metal Controlled Organic Thin Film Transistor (MC-OTFT). The performed 2D simulation study has revealed that the proposed MC-OTFT shows significantly higher sensitivity for different dielectric constants and their related charge densities. Besides, the calibrated simulation study has shown that the change in ON current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> sensing factor calculated for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =- 1.5V, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> =-3 V) in MC-OTFT is significantly higher (max. of 44.40 times for neutral, 44.55 times for charged biomolecule at ρ = - 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ). In addition, a considerable enhancement in sensitivity at low temperatures has been observed. The proposed device therefore offers a huge potential for biosensing applications.

Fluorine-based plasma treatment for hetero-epitaxial β-Ga2O3 MOSFETs

In this work, we demonstrate the lateral metal–oxidesemiconductor field-effect transistors (MOSFETs) with β-Ga2O3 film (thickness = 150 nm) grown on a c-plane sapphire substrate by a hydride vapor phase epitaxy (HVPE) method using a CF4-based plasma treatment. By incorporating fluorine (F) the electrical characteristics of the surface and bulk regions of the resistive β-Ga2O3 film could be significantly improved. The analyses by secondary ion mass spectrometry and x-ray photoemission spectroscopy confirmed the formation of the substitutional fluorine, FO, with its peak concentration of 2.3 × 1018 cm−3 at 5 ~ 10 nm deep from the surface and about 1015 ~ 1016 cm−3 in the bulk region. While the argon-plasma treatment was insufficient for making a Ti/Au/Ti metal contact ohmic, the same contact formed on the CF4-treated surface showed an ohmic behavior with specific resistivity of 2.0 × 10−3 Ω·cm2 and contact resistance of 0.8 Ω·m without any post thermal annealing. With the improvement of the electrical properties in both the surface and bulk regions, the HVEP-grown hetero-epitaxial β-Ga2O3 MOSFET exhibited the field-effect mobility of up to 5.3 cm2/V⋅s and on/off ratio of 106.

A Ultra-Low Specific On-Resistance and Extended Gate SJ LDMOS Structure

A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region. Gate oxide and silicon layer form the EG Structure-Oxide-Semiconductor structure that is similar to Metal–Insulator–Semiconductor capacitor. The the N-drift of the EG structure can obtain the charge compensation to overcome the SAD effect, and a nearly rectangular electric field is achieved. In the on-state, the EG structure has two conductive channels and the accumulation layer is formed on the drift region. By accumulating high concentration electrons in the channels, the specific on-resistance (RON,sp) is greatly reduced. When the drift length is 24 μm, 431.4 V breakdown voltage (VB) and 9.8 mΩ cm2 RON,sp are achieved, and the figure of merit is 18.9 MW cm−2.

Local Electronic Properties of Coherent Single-Layer WS2/WSe2 Lateral Heterostructures.

Lateral single-layer transition metal dichalcogenide (TMD) heterostructures are promising building blocks for future ultrathin devices. Recent advances in the growth of coherent heterostructures have improved the structural precision of lateral heterojunctions, but an understanding of the electronic effects of the chemical transition at the interface and associated strain is lacking. Here we present a scanning tunneling microscopy study of single-layer coherent TMD heterostructures with nearly uniform strain on each side of the heterojunction interface. We have characterized the local topography and electronic structure of single-layer WS2/WSe2 heterojunctions exhibiting ultrasharp coherent interfaces. Uniform built-in strain on each side of the interface arising from lattice mismatch results in a reduction of the bandgap of WS2. By mapping the tunneling differential conductance across the interface, we find type-II band alignment and an ultranarrow electronic transition region only ∼3 nm in width that arises from wave function mixing between the two materials.

A Lateral Power p-Channel Trench MOSFET Improved by Variation Vertical Doping

An improved lateral power p-channel trench metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed. By using a technique of variation vertical doping (VVD), the threat of charge imbalance posted by the parasitic trench capacitance is eliminated. Moreover, a p-type VVD increases the number of carriers, and an n-type VVD intensifies the charge compensation effect. Hence, compared to the conventional device without VVD, the proposed device gets a significantly improved tradeoff relationship between the breakdown voltage (BV) and the specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},SP}$ ). According to the simulation results, the proposed device using the triple piecewise VVD obtains a ${R}_{ \mathrm{\scriptscriptstyle ON},SP}$ of 10.6 $\text{m}\Omega \cdot $ cm2 at a BV of 440 V, reaching a figure of merit (FOM = BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},SP}$ ) being 2.4 times larger than that of the prior art.

Tunable Electronic Properties of Lateral Monolayer Transition Metal Dichalcogenide Superlattice Nanoribbons.

The structural stability and structural and electronic properties of lateral monolayer transition metal chalcogenide superlattice zigzag and armchair nanoribbons have been studied by employing a first-principles method based on the density functional theory. The main focus is to study the effects of varying the width and periodicity of nanoribbon, varying cationic and anionic elements of superlattice parent compounds, biaxial strain, and nanoribbon edge passivation with different elements. The band gap opens up when the (MoS2)3/(WS2)3 and (MoS2)3/(MoTe2)3 armchair nanoribbons are passivated by H, S and O atoms. The H and O co-passivated (MoS2)3/(WS2)3 armchair nanoribbon exhibits higher energy band gap. The band gap with the edge S vacancy connecting to the W atom is much smaller than the S vacancy connecting to the Mo atom. Small band gaps are obtained for both edge and inside Mo vacancies. There is a clear difference in the band gap states between inside and edge Mo vacancies for symmetric nanoribbon structure, while there is only a slight difference for asymmetric structure. The electronic orbitals of atoms around Mo vacancy play an important role in determining the valence band maximum, conduction band minimum, and impurity level in the band gap.

Breakdown point transfer theory for Si/SiC heterojunction LDMOS with deep drain region

Abstract Heterojunction terminal technology, especially Si/SiC heterojunction, has been widely used in the power semiconductor device. Si/SiC heterojunction LDMOS combines the advantages of Si and SiC while the breakdown point is transferred due to employing the deep drain region structure to improve the BV of the device. Based on the existing research, a new theory about breakdown point transfer terminal technology is proposed for silicon on silicon carbide lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region based on the electric field modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the breakdown voltage and electric field (E-field) distributions of Si/SiC LDMOS. The mechanism of surface electric field modulated and optimized by breakdown point transfer terminal technology is explained. Introducing the drain region impact factor into the analytical model to decouple the lateral and vertical depletion below the drift region. The analytical model proves that the deep drain region structure can modulate both the lateral and vertical electric field. Meanwhile, the location of the breakdown point can be determined by the E-field distribution at y = TDr and the E-field distribution at y = TSi, which is demonstrated by both theoretical interpreting and simulation. The derivations were verified using the ISE TCAD with a good agreement in the analytical model by changing the key structural parameters of the device. This analytical theory can be applied to other heterojunction power devices.

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

In this article, an improved model on buried-oxide (BOX) damage induced by total-ionizing-dose (TID) effect considering positive oxide trapped charge ( N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) generated in silicon on insulator (SOI)/BOX interface under negative electric field bias (field lines perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX) and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> saturation effect is proposed and adopted in accurate simulated analysis to predict the postirradiation device behavior. Moreover, the mechanism of high-voltage (HV) SOI lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) degradation during irradiation is also revealed by the proposed accurate simulation method. Tolerance design for radiation-hardened HV SOI LDMOS is discussed with the aid of the presented model. The tradeoff between postirradiation electrical characteristics and fresh electrical characteristics should be taken into account to meet the radiation hardening requirement. The radiation-hardened-by-design LDMOS introduced in this article keeps an OFF-state breakdown voltage above 120 V at D = 500 krad(Si) with operating voltage equal to 80 V, which is fabricated on a commercial SOI substrate material with plain interface quality parameters. The corresponding hardening strategy is also given.

Analysis of novel silicon based lateral power devices with floating substrate on insulator

With the rapid development of the traditional inorganic semiconductor industry, the improvement of its electrical performance is gradually approaching to the limit. It is difficult to continue to improve the performance, lessen the size, and reduce the cost. Therefore, organic semiconductor materials and devices with simple process and low cost have been found and gradually become a new research hotspot. Although organic semiconductor materials and devices are developing rapidly, their electrical properties, such as carrier mobility, are considerably inferior to those of inorganic semiconductors, and their research direction and application prospect are relatively fixed and single. They are developed only in display, sensing, photoelectric conversion and other fields, but the researches on switching power devices, integrated circuits and other fields are still relatively blank. At the same time, power devices are used only in the field of inorganic semiconductors. Therefore, in order to expand the research direction of organic semiconductors and power devices at the same time, a novelsilicon on insulator lateral double-diffused metal oxide semiconductor (SOI LDMOS)power device is reported in this paper. Unlike the SOI LDMOS power devices in traditional inorganic semiconductors, this novel device can be used in the field of organic semiconductors by combining with insulated flexible substrates, which provides a new possibility for the research direction of organic semiconductors. In this paper, both simulation and experiment verify that specific on-resistance (&lt;i&gt;R&lt;/i&gt;&lt;sub&gt;ON,sp&lt;/sub&gt;) and threshold voltage (&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;TH&lt;/sub&gt;) do not change significantly when the conventional SOI LDMOS lacks the substrate electrode, but the breakdown voltage decreases by about 15% due to the absence of the substrate electrode or the longitudinal electric field. In response to this phenomenon, in this paper proposed is a novel SOI LDMOS power device that possesses surface substrate electrodes and drift zone oxide trenches. This novel device can provide electrodes for the substrate again, optimize the horizontal and vertical electric field, and significantly change neither of the &lt;i&gt;R&lt;/i&gt;&lt;sub&gt;ON,sp&lt;/sub&gt; and the &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;TH&lt;/sub&gt;. At the same time, the breakdown voltage (BV) of conventional SOI LDMOS is increased by 57.54%, which alleviates the adverse effects caused by the application in the field of organic semiconductors. This novel SOI LDMOS power device provides the possibility of applying traditional power semiconductors to the research of organic semiconductors, and has innovative significance for expanding the organic semiconductor research.

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

A novel Si/SiC heterojunction Lateral Double-diffused Metal Oxide Semiconductor with the Semi-Insulating Polycrystalline Silicon field plate (SIPOS Si/SiC LDMOS) is proposed in this paper for the first time. The innovative terminal technology of Breakdown Point Transfer (BPT) had been applied on Si/SiC MOSFETs. This creative technology improved Breakdown Voltage (BV) of the proposed device, compared with the conventional Si LDMOS (Cov. LDMOS). In order to optimize the trade-off between BV and Specific On-Resistance (RON,SP), the SIPOS field plate is applied on Si/SiC LDMOS for the first time in this paper. At On-State, due to the internal electric field of SIPOS filed plate, the majority carriers accumulation layer is formed on the surface of the drift region for the proposed SIPOS Si/SiC LDMOS, which means RON,SP will be reduced. Meanwhile, the electric field modulation effect of SIPOS field plate can make the surface electric field distribute evenly, which leads to an increase of BV. In addition, due to the high-thermal conductivity of SiC substrate, the heat-dissipation efficiency of the proposed device is significantly improved. The simulation results show that the BV of SIPOS Si/SiC LDMOS is 428.4V, which increased by 78.4% in comparison with Cov. LDMOS (BV of 240.0V) with the same structure parameters. The R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,SP</sub> of SIPOS Si/SiC LDMOS is decreased from 33.2mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of Cov. LDMOS to 24.0mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , decreased by 27.7%. Furthermore, the figure-of-merit (FOM = BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of SIPOS Si/SiC LDMOS reaches 7.6MW/cm2, which means SIPOS Si/SiC LDMOS has enough performance to break the Silicon limit.

Novel Si/SiC heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit* *Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017) and the 111 Project (Grant No. B12026).

A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (R on,sp). Through TCAD simulation, when the drift region length is 20 μm, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μm, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit.

A compact and low-driving-voltage silicon electro-absorption modulator utilizing a Schottky diode operating up to 13.2 GHz in C-band

This paper demonstrates a 1 Vpp low-driving-voltage silicon electro-absorption modulator (EAM) utilizing a Schottky diode. Optical modulation using a Schottky diode was achieved through the intensity change of the guiding light due to free-carrier absorption in the semiconductor to change its absorption coefficient, not through conventional interference effects. The proposed EAM consists of a lateral metal–semiconductor junction that helps maximize free-carrier injection and extraction through a Schottky contact on rib waveguide. In order to achieve high-speed operation, traveling-wave type electrodes were designed. The fabricated EAM demonstrates a broad operational wavelength range of 50 nm for C-band with a uniform extinction ratio (ER) of 3.9 dB, even for a compact modulation length of 25 μm with a driving voltage of 1 Vpp. Also, the traveling-wave type electrodes enabled the modulator to operate at up to 26 GHz with 13.2 GHz of 3 dB electro-optic bandwidth experimentally.

Dispersion effects in on‐state resistance of lateral Ga 2 O 3 MOSFETs at 300 V switching

Static characterisation and fast switching processes of lateral β-Ga2O3 metal oxide semiconductor field-effect transistors (MOSFETs) are presented. The investigated transistors with 10 mm gate width and 6 µm gate drain distance achieve on-state resistances of 5 Ω and saturation currents above 2.4 A. Hard switching in a double pulse test setup with an inductive load results in voltage slopes up to 65 V/ns at 300 V input voltage. After longer blocking times and higher DC voltages, a strong dynamic increase in on-state resistance occurs. Switching with an ohmic load and different load currents reveals only minor influence of the hot electron mechanism during the hard turn on. However, a clear influence of the turn-on gate drive voltage on the dynamic increase is observed, indicating a shift of the transfer characteristic due to charge trapping in the gate region.

Mechanism of lateral metal flow on residual stress distribution during hot strip rolling

During hot strip rolling, the lateral metal flow can change the longitudinal residual stress to reduce the risk of buckling deformation of the strip. The mechanism of lateral metal flow on residual stress was studied by combining a residual stress model with experimentation. A buckling risk coefficient was proposed to quantify the risk of buckling deformation. The calculated results show that the lateral metal flow has a self-correcting effect on the residual stress caused by the change in unit crown, this is, metals preferentially flow towards the direction helping reduce the maximum residual compressive stress. Changes in width and thickness of the strip induce a large difference in the attenuation of the maximum residual compressive stress even if the unit crown has the same change. For instance, under a large reduction rate the mode of residual stress may change from the edge-waves to the W-waves mode. A novel rolling experiment was developed, in which the grid method was employed to capture the tiny metal flow along the width. The measured lateral metal flow law is consistent with the description of the self-correcting effect of the lateral metal flow.

Fabrication and characterization of Cu2O/Cu-WO3 bilayers for lateral programmable metallization cells

Lateral Programmable Metallization Cell (PMC) structures rely on metal electrodeposition in a long channel consisting of a solid electrolyte layer between an anode and a cathode. Integration of these devices with CMOS circuitry demands using materials such as copper and tungsten for the electrodes, and an oxide of tungsten (WO3) doped with Cu for the electrolyte. However, low diffusivity of Cu in WO3 and its high resistivity results in a slow electrodeposition process. Our solution to this problem involves the use of a Cu2O/Cu-WO3 bilayer, formed by oxidation of a thin Cu film on a WO3 layer and a simultaneous diffusion of Cu into the WO3 at moderate temperatures. This creates a Cu-WO3 solid electrolyte with a semiconducting Cu2O coating that brings electrons to where the ions are most abundant and thereby greatly increases the electrodeposition rate. In this paper, an investigation of thin film Cu oxidation is presented along with the diffusion kinetics of Cu in WO3. The Cu was oxidized in air to form Cu2O with an activation energy of 0.70 eV. The diffusion analysis showed activation energy of Cu diffusion in WO3 was 0.74 eV, which we believe is the first time this value has been reported.

Four-terminal polycrystalline Ge1−xSnx thin-film transistors using copper-induced crystallization on glass substrates and their application to enhancement/depletion inverters

Polycrystalline germanium–tin (Ge1−xSnx) thin films with a thickness of 15 nm were grown at 500 °C using Cu-induced crystallization. The films were applied to fabricate four-terminal (4T) thin-film transistors (TFTs) on a glass substrate. The top gate (TG) was fabricated from 30 nm thick SiO2, while the bottom gate (BG) consisted of a double layer of HfO2 and SiO2 with a capacitance equivalent thickness of 16 nm. Aluminum-induced lateral metallization of the source and drain (SD) was implemented to decrease the parasitic resistance of the SD. The Ion/Ioff of the double gate approximately corresponded to 1 × 104. Furthermore, 4T poly-Ge1−xSnx TFTs operated with a field-effect mobility of 20 cm2 V−1 s−1 for the TG drive and 12 cm2 V−1 s−1 for the BG drive at a control gate voltage of 0 V in both cases. A p-channel enhancement/depletion inverter was validated based on the precise control of threshold voltage using a control gate.

Preparation of Functionalized Aryl, Heteroaryl, and Benzylic Potassium Organometallics Using Potassium Diisopropylamide in Continuous Flow.

We report the preparation of lithium‐salt‐free KDA (potassium diisopropylamide; 0.6 m in hexane) complexed with TMEDA (N,N,N′,N′‐tetramethylethylenediamine) and its use for the flow‐metalation of (hetero)arenes between −78 °C and 25 °C with reaction times between 0.2 s and 24 s and a combined flow rate of 10 mL min−1 using a commercial flow setup. The resulting potassium organometallics react instantaneously with various electrophiles, such as ketones, aldehydes, alkyl and allylic halides, disulfides, Weinreb amides, and Me3SiCl, affording functionalized (hetero)arenes in high yields. This flow procedure is successfully extended to the lateral metalation of methyl‐substituted arenes and heteroaromatics, resulting in the formation of various benzylic potassium organometallics. A metalation scale‐up was possible without further optimization.

Numerical Study of Graphene Heat Spreaders for a THz Quantum Diode Based on a G-MGIM Junction

In the context of a numerical study about mid-infrared receivers based on a metal–insulator–metal junction, we study how a top multilayer of graphene is capable to remove heat from the thin metal layer in which the laser impinges on. Due to its extremely high thermal conductivity, the graphene film (made of several layers) extracts the heat and injects it inside bulky lateral metal paddings of the receiver. Therefore, the lateral metal contacts not only detect the electromagnetic field transforming it into a current through this quantum diode, but they can also help to drain the heat. A metal–insulator–metal junction, which combines Kretschmann illumination and a distributed light on the junction (or are illuminated through a grating), allows introducing the electromagnetic field into the junction, biasing in this manner the insulator all along its entire length. The main challenge is the relationship between the insulator thickness and the electromagnetic wavelength. In the mid-infrared region, the insulator thickness of a few nanometers is several orders of magnitude under the diffraction limit, and the electromagnetic field cannot penetrate directly into the structure. In this way, the described technique delivers the infrared radiation into the junction by means of surface-plasmon-polariton traveling wave (SPP-TW). Therefore, a right illumination improves the diode responsivity considerably. However, rectification demands an extremely asymmetrical current–voltage curve. A layered metal–graphene–insulator–metal makes this feasible especially when an SPP-TW, between the graphene and the insulator, establishes a Seebeck effect resulting in the desired asymmetric characteristic. When sampling, the rectified direct tunneling current is desirable to avoid thermionic emission (inherently slow), as well as to induce the SPP-TW in a better form from the outside of the junction. A cooling mechanism that preserves a high electric conductivity on the top metal contact is required. In this theoretical work, we performed a simulation study of how a sheet of graphene is able to enhance the thermal behavior of the receiver under study.

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

Variable-K double trenches SOI LDMOS with high-concentration P-pillar**Project supported by the Scientific Research Fund of Hunan Provincial Education Department, China (Grant No. 19K001).

A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal–oxide–semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (Ron,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ⋅cm2. The Ron,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.