Lateral Insulated Gate Bipolar Transistor Research Articles

A 800 V dual conduction paths segmented anode LIGBT with low specific on-resistance and small shift voltage

A dual conduction paths segmented anode lateral insulated-gate bipolar transistor (DSA-LIGBT) which uses triple reduced surface field (RESURF) technology is proposed. Due to the hybrid structures of triple RESURF LDMOS (T-LDMOS) and traditional LIGBT, firstly, a wide p-type anode is beneficial to the small shift voltage (VST) and low specific on-resistance (Ron,sp) when the anode voltage (VA) is larger than VST. Secondly, a wide n-type anode and triple RESURF technology are used to get a low Ron,sp when VA is less than VST. Meanwhile, it can accelerate the extraction of electrons, which brings a low turn-off time (Toff). Experimental results show that: VST is only 0.9 V, Ron,sp (Ron × Area) are 11.7 and 3.6 Ω·mm when anode voltage VA equals 0.9 and 3 V, respectively, the breakdown voltage reaches to 800 V and Toff is only 450 ns.

The Hot-Carrier-Induced Degradation of SoI LIGBT Under AC Stress Conditions

The hot-carrier-induced degradation of silicon-on-insulator (SoI) lateral insulated gate bipolar transistor (LIGBT) under various ac stress conditions has been investigated. The gate voltage of the SoI LIGBT is pulsed with different frequencies, duty cycles, and rise/fall times, while a constant voltage is applied at the collector. Experiments show that the RON degradation is enhanced by increasing the gate pulse stress frequency. In addition, large duty cycle with fixed gate pulse stress frequency produces more severe RON degradation. Furthermore, the influence of the pulse rise/fall times on the RON degradation is also studied. It has been discovered that the short pulse rise/fall times imply much more serious hot-carrier degradation. Based on the experiments and simulations, several possible dynamic degradation mechanisms are proposed.

Effect of Bandgap Narrowing on Performance of Modern Power Devices

The effect of the bandgap narrowing (BGN) on performance of power devices is investigated in detail in this paper. The analysis reveals that the change in the energy band structure caused by BGN can strongly affect the conductivity modulation of the bipolar devices resulting in a completely different performance. This is due to the modified injection efficiency under high-level injection conditions. Using a comprehensive analysis of the injection efficiency in a p-n junction, an analytical model for this phenomenon is developed. BGN model tuning has been proved to be essential in accurately predicting the performance of a lateral insulated-gate bipolar transistor (IGBT). Other devices such as p-i-n diodes or punch-through IGBTs are significantly affected by the BGN, while others, such as field-stop IGBTs or power MOSFETs, are only marginally affected.

Small-sized silicon-on-insulator lateral insulated gate bipolar transistor for larger forward bias safe operating area and lower turnoff energy

This Letter presents a novel small-sized lateral insulated gate bipolar transistor on silicon-on-insulator substrate (SOI-LIGBT), which features a lowly doped p -type pillar alongside the oxide trench in the drift region. The variation in vertical doping termination technology is also proposed for the first time. The p -pillar layer leads to electric field reshaping in the y -direction, and homogenises current flow lines under the gate and cathode. It results in a very wide forward bias safe operating area (FBSOA) for the proposed SOI-LIGBT, which is obviously improved by over 50% compared with the deep-oxide trench SOI-LIGBT (DT SOI-LIGBT). Moreover, at the same forward voltage drop of 1 V, the turnoff energy loss for the proposed SOI-LIGBT is reduced by 28.5 and 81.2% compared with those of DT SOI-LIGBT and the conventional SOI-LIGBT, respectively.

200 V Superjunction N-Type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of 2 V at 300 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The latch-up current density is 1100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> . The latest design shows a latch-up current density of 1195 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The enhanced robustness against static latch-up leads to a better forward bias safe operating area.

Model of hot‐carrier degradation for lateral IGBT device on SOI substrate

A novel model for hot-carrier degradation in a lateral insulated gate bipolar transistor (IGBT) device on SOI substrate (SOI-LIGBT) is presented. The setup of the model is based on the existing hot-carrier degradation mechanism in a SOI-LIGBT and assisted by a lateral DMOS device on SOI substrate (SOI-LDMOS) with completely the same structure except for the doping type in the drain area. The model parameters have been extracted by the degradation measurement results and the validity of the proposed model in a SOI-LIGBT has been also verified.

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage (> 600 V) integrable silicon-on-insulator (SOI) trench-type lateral insulated gate bipolar transistor (LIGBT) with a reduced cell-pitch is proposed. The LIGBT features multiple trenches (MTs): two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX). Firstly, the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si. Secondly, oxide trenches bring in multi-directional depletion, leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field (RESURF) effect. Both increase the breakdown voltage (BV). Thirdly, oxide trenches fold the drift region around the oxide trenches, leading to a reduced cell-pitch. Finally, the oxide trenches enhance the conductivity modulation, resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop (Von). The oxide trenches cause a low anode—cathode capacitance, which increases the switching speed and reduces the turn-off energy loss (Eoff). The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm, a Von of 1.03 V at 100 A/cm−2, a turn-off time of 250 ns and Eoff of 4.1×10−3 mJ. The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits, simplifying the fabrication processes.

Demonstration of Lateral IGBTs in 4H-SiC

Lateral insulated gate bipolar transistors (IGBTs) in 4H-SiC are demonstrated for the first time. The devices were fabricated based on three different designs to investigate the effects of buffer doping and carrier lifetime on device performance. Experimental results show that, with a lightly doped buffer, a short drift region length, and an improved carrier lifetime, the common base current gain of the parasitic bipolar junction transistor (BJT) is improved, leading to a higher current capability of the IGBT. The differential on-resistance of the lateral IGBT with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ld</i> = 20 μm is smaller than that of a lateral MOSFET counterpart, implying partial conductivity modulation in the drift region.

The Study of Improving High Voltage LIGBT Substrate Leakage Current

This paper aims to the research of high voltage lateral insulated gate bipolar transistor (LIGBT) and proposes the design for reducing the substrate leakage current of this device. The junction between LIGBT’s p-type substrate and n-epi layer may have a large electrical field and causes the hole current to flow during the turn-on state. To prevent this substrate leakage current, an n-type buried layer (NBL) and a p-type buried layer (PBL) are used. The double reverse biased pn-junction structure effectively reduces the vertical electric field such that the substrate current is reduced by four orders of magnitude. The break down voltage of the LIGBT is not hurt by this added structure at all.

200-V Lateral Superjunction LIGBT on Partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an Rdson of 765 mΩ·mm2. It exhibits half the value of specific on-state resistance Rdson and three times higher saturation current (Idsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in Rdson at 175 °C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process.

Extraction Enhanced Lateral Insulated Gate Bipolar Transistor: A Super High Speed Lateral Insulated Gate Bipolar Transistor Superior to Lateral Dobule Difused Metal Oxide Semiconductor Field-Effect Transistor

We have successfully developed novel extraction enhanced lateral insulated gate bipolar transistors (E2LIGBTs) in conventional silicon on insulator (SOI) wafers, which exhibit super-high speed switching of 34 ns turn-off time and a low on-state voltage of 3.7 V at 84 A/cm2 simultaneously with a high breakdown voltage of 738 V. This is the first report showing its superior switching speed and on-resistance compared to conventional lateral double diffused metal oxide semiconductor field-effect transistor (LDMOS). The superior performance is achieved by a new anode structure designed with the proposed E2 concept, which simultaneously achieves enhanced electron extraction and suppression of hole injection at the anode region without life time control. The E2 concept is realized using the anode structure, consisting of a narrow p+-injector and a wide Schottky contact on a lightly doped p-layer over an n-buffer. The switching speed can be controlled by the area ratio of the Schottky area over the injector area.

Extraction Enhanced Lateral Insulated Gate Bipolar Transistor: A Super High Speed Lateral Insulated Gate Bipolar Transistor Superior to Lateral Dobule Difused Metal Oxide Semiconductor Field-Effect Transistor

Extraction Enhanced Lateral Insulated Gate Bipolar Transistor: A Super High Speed Lateral Insulated Gate Bipolar Transistor Superior to Lateral Dobule Difused Metal Oxide Semiconductor Field-Effect Transistor

High Voltage and High Reliability Silicon-on-Insulator Power IC Technologies and Their Application to 750 V 4.5 A Micro-Inverter IC

We have successfully developed the record high blocking voltage of 750 V and the largest current capability of 4.5 A silicon-on-insulator (SOI) micro-inverter IC, which is made possible by the newly developed high voltage reliability technology and high-speed and low-dissipation extraction enhanced lateral insulated gate bipolar transistor (E2LIGBT). It has been found, for the first time, that the stable and reliable high blocking voltage of 760 V is assured by controlling the sheet-resistance of the polycrystalline silicon (poly-Si) layer of the scroll-shaped resistive field plate (SRFP). The high voltage and high reliability SOI power IC technology is expected as the key technology enabling 750 V 4.5 A micro-inverter IC for harsh applications such as automotive electronics.

The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection

In this paper, the detailed characterizations of the lateral insulated-gate bipolar transistor (LIGBT) for the electro- static discharge (ESD) protection of power ICs are presented. Compared with the conventional lateral DMOS with the same structure except for the anode doping type, the LIGBT shows lower triggering voltage, faster voltage-clamping speed, and much higher ESD robustness. Experimental results demonstrate that the LIGBT with runway layout achieves excellent thermal breakdown current of more than 10 A with 250-μm device width. The high ESD performance enables the LIGBT to be used as a promising ESD protection device in the power ICs.

A novel high speed lateral IGBT with a self-driven second gate

A novel lateral IGBT with a second gate on the emitter portion is presented. A PMOS transistor, driven by the proposed device itself, is used to short the PN junction at the emitter while turned off. Low on state voltage and fast turn off speed are obtained without side-effects such as snapback I—V characteristics and difficulties of process complexity. Numerical simulation results show a drop of fall time from 120 to 12 ns and no increase of on state voltage.

A Review of techniques used in Lateral Insulated Gate Bipolar Transistor (LIGBT)

The huge demand for high voltage, high current power devices on Silicon on Chip (SoC) has led to the development of Lateral Insulated Gate Bipolar Transistor (Lateral IGBT/ LIGBT), touted as the best candidate to serve these two purposes. This paper is the first to review the research works on techniques used in LIGBTs published till now. The LIGBTs are categorized into four types based on different technologies applied, mainly junction isolation (JI), silicon on insulator (SOI), partial SOI (PSOI) and membrane, and ten varieties based on their device mechanisms, such as reverse conducting, trench gate and super junction. KeywordsA SoC, LIGBT, JI, SOI, PSOI, Membrane

A novel high voltage LIGBT with an n-region in p-substrate

A novel 4 μm thickness drift region lateral insulated gate bipolar transistor with a floating n-region (NR-LIGBT) in p-substrate is proposed. Due to the field modulation from the n-region, the vertical blocking capability is enhanced and the breakdown voltage is improved significantly. Low area cost, high current capability and short turn-off time are achieved because of the high average electric field per micron. Simulation results show that the blocking capability of the new LIGBT increases by about 58% when compared with the conventional LIGBT (C-LIGBT) for the same 100 μm drift region length. Furthermore, the turn-off time is shorter than that of the conventional LIGBT for nearly same blocking capability.

A novel lateral IGBT with a controlled anode for on-off-state loss trade-off improvement

A new lateral insulated-gate bipolar transistor with a controlled anode (CA-LIGBT) on silicon-on-insulator (SOI) substrate is reported. Benefiting from both the enhanced conductivity modulation effect and the high resistance controlled electron extracting path, CA-LIGBT has a faster turn-off speed and lower forward drop, and the trade-off between off-state and on-state losses is better than that of state-of-the-art 3-D NCA-LIGBT, which we presented earlier. As the simulation results show, the ratios of figure of merit (FOM) for CA-LIGBT compared to that of 3-D NCA-LIGBT and conventional LIGBT are 1.45: 1 and 59.53: 1, respectively. And, the new devices can be created by using additional silicon direct bonding (SDB). So, from the power efficiency point of view, the proposed CA-LIGBT is a promising device for use in power ICs.

Threshold voltage degradation under high Vgs and low Vds on 200 V SOI power devices

The hot-carrier degradation behavior of the 200V lateral insulated gate bipolar transistor and lateral diffused MOS transistor both on SOI substrates (SOI-LIGBT and SOI-LDMOS) under high Vgs and low Vds is experimentally investigated. It is shown that the hot electron injection and trapping into gate oxide in the channel region will domains the degradation, which results in the positive threshold voltage (Vth) shift, however, it is very interesting that the degradation level in SOI-LIGBT device is much more serious than that in SOI-LDMOS device. Finally, an improved method to reduce the Vth degradation of SOI-LIGBT is also presented, which is adding a P-type buried layer under the source to change the hole current path. All the results have been verified by MEDICI simulations.

Novel Hot-Carrier Degradation Mechanisms in the Lateral Insulated-Gate Bipolar Transistor on SOI Substrate

The different hot-carrier degradation mechanisms of the lateral insulated-gate bipolar transistor on a silicon-on-insulator substrate (SOI-LIGBT) for different stress conditions have been experimentally investigated for the first time. For low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> , the hot hole injects and traps into the accumulation and the field oxide, particularly the bird's beak, which results in the decrease in the on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> at the early stress stage. It is interesting that the decrease level of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> in SOI-LIGBT is much more serious than that in the SOI laterally diffused metal-oxide-semiconductor with the same structure fully except for the doping type in the drain area. In addition, the buried oxide surface under the drain area also suffers from severe hot-carrier degradation. However, for high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> , only hot-electron injection into the gate oxide near the source side can be observed; there is no hot-carrier degradation to be found in both the field and buried oxides.