Lateral Double-diffused MOS Transistor Research Articles

Hot-Carrier-Induced Degradation and Optimization for 700-V High-Voltage Lateral DMOS by the AC Stress

Because of the extremely narrow dc thermal safe operating area for 700-V high-voltage lateral double-diffused MOS (LDMOS) transistor, the gate duty-cycle-accelerated ac stress was adopted to investigate its hot-carrier-induced degradations. It is found that there are different degradation mechanisms with different amplitudes of ac gate stress, including the maximum operating gate voltage ( ${V}_{{\text {gmax}}}$ ) stress and the maximum substrate current ( ${I}_{{\text {submax}}}$ ) stress. For the ${V}_{{\text {gmax}}}$ condition, the ON-resistance ( ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) decreases first and increases finally, which is attributed to two competitive degradation mechanisms. One is the hot holes injection at the bird’s beak during the gate pulse edges, and the other one is the hot electrons injection nearby the drain during the high state level of gate pulse. However, for the ${I}_{{\text {submax}}}$ stress, the dramatical injection of hot electrons nearby the source-metal edge during the high state level of gate pulse is always the main degradation mechanism, resulting in a monotonous increase of $\text {R}_{{ \mathrm{\scriptscriptstyle ON}}}$ . Moreover, the threshold voltage ( ${V}_{{\text {th}}}$ ) degradations could be neglected due to the intact channel region under the ${V}_{{\text {gmax}}}$ and ${I}_{{\text {submax}}}$ conditions. In this way, the ${I}_{{\text {submax}}}$ condition is regarded as the worst stress, and an improved device with a linear-doped buried-p-well (BP) structure beneath the P-body has been proposed to restrain the degradation under the worst stress condition.

The impact of heavy ion irradiation on the performance of novel REDI LDMOS power devices

In this paper, the impact of heavy ion irradiation on the performance of novel REDI LDMOS (RESURF Dielectric Inserted Lateral Double-diffused MOS transistor) power devices is experimentally investigated for the first time. The performance degradation of REDI LDMOS caused by micro-dose effect and displacement damage (DD) is demonstrated, and the impact of ion fluence and device geometry is analysed. Different degradation behavior occur due to the intrinsic random incident of heavy ions. The threshold voltage (Vth) of the device is barely changed after irradiation. The off-state leakage current (Ioff) of the device may increase or decrease after irradiation, which can change by up to 2 orders of magnitude. The breakdown voltage (BV) of REDI LDMOS may decrease by up to 50%. In addition, the on-resistance (Ron) and on-state current (Ion) of the device are changed by up to about 40%. Further, heavy ion fluence has significant effect on device characteristics after irradiation. For low-fluence (5 × 108 ions cm−2), the degradation of BV is the main problem caused by irradiation. And BV, Ron and Ion degradation should be paid attention for devices irradiated by high-fluence (5 × 109 ions cm−2) heavy ion. Besides, the distance between p+ region and the drift region boundary (LD) has negligible effect on the performance degradation of the irradiated device. However, the maximum value and variation of BV degradation of devices irradiated by high-fluence heavy ion increase with the increase of the length of the gate overlap the drift region (Lov). The results are of great significance for the research of the radiation-hardened technology of power devices.

A Review on Hot-Carrier-Induced Degradation of Lateral DMOS Transistor

With the scaling of process node and increase of operation voltage, the electrical fields and impact ionization generation rates in lateral double-diffused MOS (LDMOS) transistors are obviously increased. As a result, a detailed characterization and understanding for long-term hot-carrier-induced (HCI) effect of LDMOS have been becoming more and more important. This review compares and summarizes the HCI damage locations and degradation mechanisms for all kinds of typical LDMOS devices under different stress conditions. Finally, generalized conclusions on HCI effect of LDMOS are deduced, and some special degradation influence factors brought by the device design technologies are also clarified.

Hot-Carrier Degradation in Power LDMOS: Selective LOCOS- Versus STI-Based Architecture

In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are investigated by means of constant voltage stress measurements and TCAD simulations. In particular, the on-resistance degradation in linear regime is experimentally extracted and numerically reproduced under different stress conditions. A similar amount of degradation has been reached by the two architectures, although different physical mechanisms contribute to the creation of the interface states. By using a recently developed physics-based degradation model, it has been possible to distinguish the damage due to collisions of single high-energetic electrons (single-particle events) and the contribution of colder electrons impinging on the silicon/oxide interface (multiple-particle events). A clear dominance of the single-electron collisions has been found in the case of LOCOS structure, whereas the multiple-particle effect plays a clear role in STI-based device at larger gate-voltage stress.

120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process

In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark specific on-resistance with breakdown voltage over 120 Volts. The key feature of this novel device is linear p-top rings which are located in the n-drift region. Optimization of p-top mask design and n-drift region concentration is performed in order to achieve the lowest on-resistance possible with the desired breakdown voltage.

Determination of active oxide trap density and 1/f noise mechanism in RESURF LDMOS transistors

The physical origin of majority charge carrier fluctuations in the SiO2 interface of Si at accumulation has been investigated and analyzed for differently processed and voltage-rated reduced surface field (RESURF), lateral-double-diffused MOS (LDMOS) transistors. Surface carrier mobility fluctuation due to remote Coulomb scattering by the trapped charge in the gate oxide is identified as the dominant physical mechanism for LDMOS 1/f noise irrespective of process technologies. A significant contribution to the measured noise has been noted from the surface majority carrier mobility fluctuation due to trapped charge at the accumulation region of the extended drain region, dominant over other sources including the surface minority charge carrier fluctuations in the channel. Active oxide trap density was characterized spatially and for the first time up to ∼0.4eV above the conduction band-edge of Si. The interface trap density in the unstressed devices (∼8×106cm−2) increased more than an order of magnitude (∼1×108cm−2) after the devices were stressed for 10,000sec at their individual worst drain current and on-resistance degradation conditions. The extracted Si/SiO2 interface trap density above the silicon conduction band edge was found to be several orders of magnitude lower than that reported for silicon mid-gap energies, even after stressing. Since the traps near the quasi-Fermi level for electrons are active in trapping–detrapping, and the Fermi level is energetically positioned above the conduction band edge of Si in the investigated devices as compared to the previously reported observations, the lower trap density obtained here is an indication for reversal of the well-known exponential trap energy distribution beyond the conduction band-edge of Si. These findings shift the focus from the channel to the gate overlap section of the extended drain and the quality of the Si/SiO2 interface in that region.

ESD robustness concern and optimization for high-voltage p-type LDMOS transistor with thin gate oxide used as the output driver

The p-type lateral double-diffused MOS (pLDMOS) transistor with thin gate oxide has significant advantages when being used as a high side output driver in high-voltage ICs (HVICs), because it usually possesses larger current density compared with a device with thick gate oxide. However, in order to reduce the chip size, many HVICs do not have specialized output electrostatic discharge (ESD) protection cells, so the pLDMOS device is operated both as the output driver and the ESD protection structure. In this work, we have found that the ESD robustness of the pLDMOS with thin gate oxide is poor. As a result, this device is risky for those area-efficient HVICs. To solve the contradiction, the inner mechanism of the poor ESD robustness for the pLDMOS with thin gate oxide has been investigated. Moreover, an improved method, by adjusting the overlap length between the special p-well and the source p+ implantation region, has been presented. The experimental results show that the ESD robustness of the improved pLDMOS with thin gate oxide has been obviously increased, while the large current density can be also maintained.

A Low-Cost 900V Rated Multiple RESURF LDMOS Ultrahigh-Voltage Device MOS Transistor Design without EPI Layer

In this paper, a low-cost 900V rated multiple RESURF lateral double-diffused MOS (LDMOS) transistor in junction-isolated power IC technology without EPI layer is developed and successfully simulated. Don't think that the bigger the processing node the lower the cost. There are LDMOS processes today at the 0.35-micron node that use the same number of masks that are required at the 1.0-micron node. Moreover, smaller processing nodes yield smaller chip sizes, which carry both performance and cost benefits. Evaluate EPI vs. non-EPI wafers, and if your performance requirements can be met with non-EPI that is the best choice for lower cost implementation. Detailed device simulations and structure designs have been done. The optimized devices show excellent performance, which have been demonstrated with characterization results from device. The proposed multiple RESURF LDMOS without EPI Layer is able to achieve a specific on-resistance of lower than 250 mΩ-cm2 while maintaining a breakdown of over 900 volts.

Anomalous Hot-Carrier-Induced Linear Drain Current Degradation of LDMOS Under Pulse Gate Stress With Different Amplitudes

In this letter, the hot-carrier-induced linear drain current degradations of the n-type lateral double-diffused MOS (LDMOS) transistor under the pulse gate stress with different amplitudes and the worst dc gate stress are experimentally compared. They show that the degradation under the 1.5 V pulse gate stress is less than that under the worst dc gate stress (1.5 V). However, under the 5 V pulse gate stress, the degradation is about two times larger than that under the worst dc gate stress because of the enhanced impact ionization at the pulse falling edge. In this way, the large gate pulse amplitude stress is used for evaluating the hot-carrier-induced lifetime of the LDMOS working with the large gate pulse.

The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs

This paper reviews the industry-standard surface-potential-based compact model HiSIM_HV for high-voltage MOSFETs, as, e.g., the lateral double-diffused MOS transistor, and introduces important improvements implemented in the second-generation model versions (HiSIM_HV2), for which open source code has been released since October 2011. HiSIM_HV solves the Poisson equation consistently within the intrinsic MOSFET, i.e., the gate-drift overlap region and the drain-side part of the drift region. Excess carrier concentrations in the drift region are accurately considered together with the velocity saturation effect. These modeling concepts enable a scalable compact model formulation with only one internal node. Fulfillment of the current continuity between MOSFET and drift parts is required for determining the internal node potential. An important enhancement implemented in the HiSIM_HV2 models is a physically accurate compact drift region resistance model, which captures the effects of the structure-dependent 2-D current flows in overlap and drift regions with their complicated bias dependence. Furthermore, compact modeling of gate overlap capacitance, leakage currents due to, e.g., impact ionization, self-heating, noise, and symmetry properties (smooth derivatives at zero drain-source voltage) have been substantially improved.

High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

High-performance p-channel lateral double-diffused MOS (LDMOS) transistors designed to operate in a wide voltage range from 35 to 200 V and built using silicon-on-insulator LDMOS platform technology were studied. A novel channel structure was applied, and consequently, a high saturation drain current of 172 μA/μm in the 200-V p-channel LDMOS transistor was achieved, which is comparable to that of an n-channel LDMOS transistor. A low on -resistance of 3470 mΩ·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35-200-V LDMOS transistors with low on-resistance were also demonstrated by optimizing the layout, i.e., the reduced surface field structure and field plates.

Compact Model of Impact Ionization in LDMOS Transistors

This paper presents a compact model of impact ionization currents in lateral double-diffused MOS (LDMOS) transistors. Depending on bias conditions, impact ionization in LDMOS transistors primarily occurs either in the intrinsic MOSFET or in the drift region, leading to a “double-hump” substrate current behavior and enhanced drain current when both VG and VD are high. Impact ionization in the drift region also causes the “expansion” effect, which is modeled by making the drift region resistance a function of the impact ionization current in the same region. The new model is verified by comparison with TCAD simulations and experimental data. The interaction between the expansion effect and self-heating is also accurately captured by the model.

SP-HV: A Scalable Surface-Potential-Based Compact Model for LDMOS Transistors

This paper introduces a scalable compact model of lateral double-diffused MOS (LDMOS) transistors. The new model, i.e., the Surface-Potential-based High-Voltage MOS (SP-HV), is constructed from a surface-potential-based bulk MOS field-effect transistor model, i.e., PSP, and a nonlinear resistor model, i.e., R3. Extensions are made to both PSP and R3 for improved modeling of LDMOS devices, and one internal node is introduced to connect the two component models. The new model is validated by comparison to technology computer-aided design (TCAD) simulations and experimental data. Quasi-saturation, self-heating, impact ionization current in the drift region, and complex behavior of transcapacitances are accurately modeled by SP-HV.

Improving Breakdown Behavior by Substrate Bias in a Novel Double Epi-layer Lateral Double Diffused MOS Transistor

A new lateral double diffused MOS (LDMOS) transistor with a double epitaxial layer formed by an n-type substrate and a p-type epitaxial layer is reported (DEL LDMOS). The mechanism of the improved breakdown characteristic is that the high electric field around the drain is reduced by substrate reverse bias, which causes the redistribution of the bulk electric field in the drift region, and the vertical blocking voltage is shared by the drain side and the source side. The numerical results indicate that the trade-off between breakdown voltage and on-resistance of the proposed device is improved greatly in comparison to that of the conventional LDMOS.

A compact model for the ion implanted channel LDMOS transistor

This paper presents a compact model for the lateral double-diffused MOS transistor in which ion implantation is employed in the channel region. We show that the conventional LDMOS device models which do not include specifics of the implanted channel region cannot accurately predict behavior of such structure. We then propose a new physics based model which employs surface potential in the device. The model gives a robust formulation for both the channel and the drift regions and can accurately describe the performance of the ion implanted channel LDMOS structure.

A novel thin drift region device with field limiting rings in substrate

A novel thin drift region device with heavily doped N+ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor (SFLR LDMOS). In the SFLR LDMOS, the peak of the electric field at the main junction is reduced due to the transfer of the voltage from the main junction to other field limiting ring junctions, so the vertical electric field is improved significantly. A model of the breakdown voltage is developed, from which optimal spacing is obtained. The numerical results indicate that the breakdown voltage of the device proposed is increased by 76% in comparison to that of the conventional LDMOS.

Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon

In this paper, a new power metal-oxide-semiconductor field-effect transistor (MOSFET) with a FS surface to reduce the specific on-resistance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is proposed. Semi-insulating polycrystalline silicon (SIPOS) is deposited over a thin oxide layer. Drift-region concentration is higher in the proposed device than that of conventional lateral double-diffused MOS (LDMOS), and its structure with SIPOS is compared at the same breakdown voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> . In the proposed MOSFET, the effect of electric-field modulation is improved, when compared with an accumulation LDMOS transistor (ALDMOST) due to a complete 3-D reduced surface-field effect. An extra multilayer majority carrier is introduced on the sidewalls of the trench, which reduces <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of the drift region. This indicates that the ideal silicon limit of the tradeoff of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> has been broken due to the lowest <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> value in the proposed MOSFET. In the proposed MOSFET, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> (i.e., 13.5 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> (i.e., 440 V) are improved greatly, when compared with the ALDMOST (i.e., with an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of 26 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> of 400 V) and a superjunction structure (i.e., with an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of 98 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> of 410 V).

ESD robustness improvement for integrated DMOS transistors —the different gate‐voltage dependence of It2 between VDMOS and LDMOS transistors

AbstractThis paper presents the device‐level electrostatic discharge (ESD) robustness improvement for integrated vertical double‐diffused MOS (VDMOS) and lateral double‐diffused MOS (LDMOS) transistors by changing device structure. The ESD robustness of VDMOS transistor was improved by preventing current concentration and that of LDMOS transistor was improved by relaxing the electric field under the LOCOS oxide. We found the different gate‐voltage dependence of the second breakdown current (It2) between VDMOS and LDMOS transistors. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology

An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-μm 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.

Analysis and modeling of quasi-saturation effect in high-voltage LDMOS transistors

This paper investigates a specific current saturation phenomenon in high-voltage LDMOS (lateral double-diffused MOS) transistors, i.e., the quasi-saturation effect. By means of simulation tool TCAD, we clarified that the physical mechanism of quasi-saturation effect is the carrier velocity saturation in the drift region. Further more, with the concept of intrinsic drain voltage Vk, a mathematical model is derived to describe the current saturation effect in LDMOS transistors. The proposed model has been primarily validated by Matlab program and exhibites excellent accuracy, speed and scalability. This model can be further implemented in SPICE circuit simulation.