A Low-Cost 900V Rated Multiple RESURF LDMOS Ultrahigh-Voltage Device MOS Transistor Design without EPI Layer

Abstract

In this paper, a low-cost 900V rated multiple RESURF lateral double-diffused MOS (LDMOS) transistor in junction-isolated power IC technology without EPI layer is developed and successfully simulated. Don't think that the bigger the processing node the lower the cost. There are LDMOS processes today at the 0.35-micron node that use the same number of masks that are required at the 1.0-micron node. Moreover, smaller processing nodes yield smaller chip sizes, which carry both performance and cost benefits. Evaluate EPI vs. non-EPI wafers, and if your performance requirements can be met with non-EPI that is the best choice for lower cost implementation. Detailed device simulations and structure designs have been done. The optimized devices show excellent performance, which have been demonstrated with characterization results from device. The proposed multiple RESURF LDMOS without EPI Layer is able to achieve a specific on-resistance of lower than 250 mΩ-cm2 while maintaining a breakdown of over 900 volts.